Regzarr's Pastebin

3,032 12,876 0 6 years ago

Name / Title	Added	Expires	Hits	Syntax
LSIC - all labs so far in Verilog	Nov 25th, 2024	Never	14	VeriLog	-
LSIC - Frequency Divider	Nov 25th, 2024	Never	12	SystemVerilog	-
LSIC - 7 segment displays	Nov 25th, 2024	Never	10	SystemVerilog	-
LSIC - Main System	Nov 25th, 2024	Never	23	SystemVerilog	-
prj.tcl (LSIC lab)	Nov 19th, 2024	Never	7	None	-
TimeMeasurement module (LSIC)	Nov 19th, 2024	Never	35	VeriLog	-
cet_Test1_reqs	Nov 5th, 2024	Never	7	None	-
cet_test1	Nov 5th, 2024	Never	6	None	-
Untitled	Mar 14th, 2023	Never	115	None	-
Untitled	Mar 14th, 2023	Never	32	None	-
ADA_l2x1	Mar 1st, 2023	Never	543	Python	-
aoc8_2022	Dec 9th, 2022	Never	968	Python	-
lab8 DSP	May 25th, 2021	Never	1,052	MatLab	-
dsp lab 7	May 13th, 2021	Never	267	MatLab	-
DSP lab10	May 4th, 2021	Never	923	MatLab	-
DSP lab9 part2	Apr 22nd, 2021	Never	1,033	MatLab	-
lab9	Apr 6th, 2021	Never	280	MatLab	-
l7 dsp	Mar 30th, 2021	Never	740	MatLab	-
l6 dsp	Mar 23rd, 2021	Never	905	MatLab	-
lab2 OS	Feb 24th, 2020	Never	243	Bash	-
ada lab 0	Feb 21st, 2020	Never	245	C	-
CORDIC method	Dec 5th, 2019	Never	190	C	-
frogs_lakes_WIP_Calin	Dec 4th, 2019	Never	207	C	-
Untitled	Nov 18th, 2019	Never	206	None	-
reg_file_16x32	Nov 7th, 2019	Never	469	VeriLog	-
dec_4s	Nov 7th, 2019	Never	143	VeriLog	-
bvd_to_e3_conv	Nov 7th, 2019	Never	520	VeriLog	-
reg_file	Oct 31st, 2019	Never	455	VeriLog	-
decoder	Oct 31st, 2019	Never	165	VeriLog	-
mux	Oct 31st, 2019	Never	413	VeriLog	-
reg	Oct 31st, 2019	Never	170	VeriLog	-
fsm_3s	Oct 24th, 2019	Never	142	VeriLog	-
tb	Oct 24th, 2019	Never	378	VeriLog	-
convo (needs fixing)	Jun 4th, 2019	Never	220	C	-
greedy	Apr 24th, 2019	Never	228	C	-
first convolution v1.1 (notepad++ indentation)	Apr 15th, 2019	Never	234	C	-
C Chess v0.12	Mar 25th, 2019	Never	264	C	-
sorting and searching	Mar 17th, 2019	Never	208	C	-
unions, structs and bit fields	Mar 12th, 2019	Never	194	C	-
Untitled	Oct 30th, 2018	Never	243	C	-
problem 2	Oct 16th, 2018	Never	215	C	-
problem 1	Oct 16th, 2018	Never	211	C	-