LSIC - all labs so far in Verilog

// FrequencyDivider
module FrequencyDivider(
    input clk_in,
    input rst,
    output reg clk_out
);

    reg [3:0] counter;

    always @(posedge clk_in or posedge rst) begin
        if (rst) begin
            counter <= 0;
            clk_out <= 0;
        end else begin
            if (counter == 9) begin
                counter <= 0;
                clk_out <= ~clk_out;
            end else begin
                counter <= counter + 1;
            end
        end
    end

endmodule

// TimeMeasurement
module TimeMeasurement(
    input clk,
    input rst,
    input [1:0] opcode,
    output [31:0] ms_count
);

    reg [22:0] clk_counter_reg, clk_counter_nxt;
    reg [31:0] ms_count_reg, ms_count_nxt;
    reg running;

    always @(posedge clk or posedge rst) begin
        if (rst) begin
            clk_counter_reg <= 0;
            ms_count_reg <= 0;
        end else begin
            clk_counter_reg <= clk_counter_nxt;
            ms_count_reg <= ms_count_nxt;
        end
    end

    always @(*) begin
        clk_counter_nxt = clk_counter_reg;
        ms_count_nxt = ms_count_reg;

        if (running) begin
            if (clk_counter_reg == 49999) begin // Verilog constant syntax unchanged
                clk_counter_nxt = 0;
                ms_count_nxt = ms_count_reg + 1;
            end else begin
                clk_counter_nxt = clk_counter_reg + 1;
            end
        end

        case (opcode)
            2'b01: running = 1;   // Start
            2'b11: running = 0;   // Pause
            2'b10: begin          // Stop
                running = 0;
                ms_count_nxt = 0;
            end
            default: running = 0; // Default state
        endcase
    end

    assign ms_count = ms_count_reg;

endmodule

// SevenSegmentController
module SevenSegmentController(
    input [31:0] ms_count,
    output reg [6:0] hex0, hex1, hex2, hex3, hex4, hex5
);

    reg [3:0] digit[5:0];

    // Function definition changed for Verilog
    function [6:0] encode;
        input [3:0] value;
        case (value)
            4'd0: encode = 7'b1000000;
            4'd1: encode = 7'b1111001;
            4'd2: encode = 7'b0100100;
            4'd3: encode = 7'b0110000;
            4'd4: encode = 7'b0011001;
            4'd5: encode = 7'b0010010;
            4'd6: encode = 7'b0000010;
            4'd7: encode = 7'b1111000;
            4'd8: encode = 7'b0000000;
            4'd9: encode = 7'b0010000;
            default: encode = 7'b1111111;
        endcase
    endfunction

    always @(*) begin
        digit[0] = ms_count % 10;
        digit[1] = (ms_count / 10) % 10;
        digit[2] = (ms_count / 100) % 10;
        digit[3] = (ms_count / 1000) % 10;
        digit[4] = (ms_count / 10000) % 10;
        digit[5] = (ms_count / 100000) % 10;

        hex0 = encode(digit[0]);
        hex1 = encode(digit[1]);
        hex2 = encode(digit[2]);
        hex3 = encode(digit[3]);
        hex4 = encode(digit[4]);
        hex5 = encode(digit[5]);
    end

endmodule

// MainSystem
module MainSystem(
    input rst,
    input clk,
    input switch_pause,
    input btn_start,
    output [6:0] hex0, hex1, hex2, hex3, hex4, hex5
);

    wire clk_2_5MHz;
    wire [31:0] ms_count;
    reg [1:0] opcode;

    FrequencyDivider freq_div (
        .clk_in(clk),
        .rst(rst),
        .clk_out(clk_2_5MHz)
    );

    TimeMeasurement timer (
        .clk(clk_2_5MHz),
        .rst(rst),
        .opcode(opcode),
        .ms_count(ms_count)
    );

    SevenSegmentController display (
        .ms_count(ms_count),
        .hex0(hex0),
        .hex1(hex1),
        .hex2(hex2),
        .hex3(hex3),
        .hex4(hex4),
        .hex5(hex5)
    );

    always @(*) begin
        opcode = 2'b00;
        if (btn_start) opcode = 2'b01;
        else if (switch_pause) opcode = 2'b11;
    end

endmodule