regzarr

dec_4s

Nov 7th, 2019
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  1. module dec_4s(
  2.   input [3:0]s,
  3.   input we,
  4.   output [15:0]o
  5.   );
  6.  
  7.   assign o = we ? (16'd1 << s) : 16'd0;
  8.  
  9. endmodule
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