mux

module mux # ( parameter k = 8 )
(
  input [k-1:0]d0, [k-1:0]d1, [k-1:0]d2, [k-1:0]d3,
  input [1:0]s,
  output reg [k-1:0]o );

  always @(*) begin
    if (s == 0)
      o <= d0;
    else if (s == 1)
      o <= d1;
    else if (s == 2)
      o <= d2;
    else
      o <= d3;
    end

endmodule