LSIC - Main System

`timescale 1ns/1ps

module MainSystem(
    input rst,              // Reset input (PIN_B8)
    input clk,              // 50 MHz clock input (PIN_P11)
    input switch_pause,     // Pause switch (PIN_C10)
    input btn_start,        // Start button (PIN_A7)
    output [6:0] hex0,      // 7-segment output for digit 0
    output [6:0] hex1,      // 7-segment output for digit 1
    output [6:0] hex2,      // 7-segment output for digit 2
    output [6:0] hex3,      // 7-segment output for digit 3
    output [6:0] hex4,      // 7-segment output for digit 4
    output [6:0] hex5       // 7-segment output for digit 5
);

    // Internal signals
    wire clk_2_5MHz;         // 2.5 MHz clock from FrequencyDivider
    wire [31:0] ms_count;    // Millisecond counter from TimeMeasurement
    reg [1:0] opcode;        // FSM opcode for TimeMeasurement

    // Instantiate FrequencyDivider
    FrequencyDivider freq_div (
        .clk_in(clk),       // Input 50 MHz clock
        .rst(rst),          // Reset input
        .clk_out(clk_2_5MHz) // Output 2.5 MHz clock
    );

    // Instantiate TimeMeasurement
    TimeMeasurement timer (
        .clk(clk_2_5MHz),    // 2.5 MHz clock input
        .rst(rst),           // Reset input
        .opcode(opcode),     // FSM control opcode
        .ms_count(ms_count)  // Millisecond counter output
    );

    // Instantiate SevenSegmentController
    SevenSegmentController display (
        .ms_count(ms_count), // Millisecond counter input
        .hex0(hex0),         // 7-segment digit 0
        .hex1(hex1),         // 7-segment digit 1
        .hex2(hex2),         // 7-segment digit 2
        .hex3(hex3),         // 7-segment digit 3
        .hex4(hex4),         // 7-segment digit 4
        .hex5(hex5)          // 7-segment digit 5
    );

    // FSM logic for opcode control
    always @(*) begin
        // Default state: no operation
        opcode = 2'b00;

        if (btn_start) begin
            opcode = 2'b01; // Start
        end else if (switch_pause) begin
            opcode = 2'b11; // Pause
        end
    end

endmodule