LSIC - Frequency Divider

module FrequencyDivider(
    input clk_in,
    input rst,
    output reg clk_out
);

    reg [4:0] counter;

    always @(posedge clk_in or negedge rst) begin
        if (!rst) begin
            counter <= 0;
            clk_out <= 0;
        end else begin
            if (counter == 9) begin
                counter <= 0;
                clk_out <= ~clk_out;
            end else begin
                counter <= counter + 1;
            end
        end
    end

endmodule