Sidsh's Pastebin

940 32,262 0 3 years ago

Name / Title	Added	Expires	Hits	Syntax
Untitled	Dec 4th, 2024	Never	5,483	SystemVerilog	-
Untitled	Dec 1st, 2024	Never	24	None	-
function cache rajni	Dec 1st, 2024	Never	192	SystemVerilog	-
Untitled	Nov 8th, 2024	Never	33	None	-
Untitled	Nov 2nd, 2022	Never	378	None	-
Reporting system	Oct 29th, 2022	Never	1,360	SystemVerilog	-
sequencer.sv	Oct 29th, 2022	Never	1,373	SystemVerilog	-
monitor.sv	Oct 29th, 2022	Never	1,439	SystemVerilog	-
driver.sv	Oct 29th, 2022	Never	1,426	SystemVerilog	-
interface.sv	Oct 29th, 2022	Never	1,306	SystemVerilog	-
sequence.sv	Oct 29th, 2022	Never	1,522	SystemVerilog	-
sequence_item.sv	Oct 29th, 2022	Never	1,467	SystemVerilog	-
agent.sv	Oct 29th, 2022	Never	1,332	SystemVerilog	-
env.sv	Oct 29th, 2022	Never	1,366	SystemVerilog	-
test.sv	Oct 29th, 2022	Never	1,309	SystemVerilog	-
top.sv	Oct 29th, 2022	Never	1,260	SystemVerilog	-
Haskell blinker.	Jun 26th, 2022	Never	436	Haskell	-
Haskell Blinker	Jun 26th, 2022	Never	186	None	-
Haskell Blinker	Jun 26th, 2022	Never	396	Haskell	-
Blinker Haskell;	Jun 26th, 2022	Never	310	Haskell	-
WB_pwmaudiocontroller	Apr 10th, 2022	Never	849	SystemVerilog	-
Counter	Mar 25th, 2022	Never	168	None	-
LSA Documented 2.0	Mar 3rd, 2022	Never	330	VeriLog	-
LED Documented (sec*) 2.0	Mar 3rd, 2022	Never	171	None	-
ADC Documented 2.0	Mar 3rd, 2022	Never	342	VeriLog	-
LSA Documented 1.1	Mar 3rd, 2022	Never	348	VeriLog	-
LED Documented (sec*)	Mar 3rd, 2022	Never	328	VeriLog	-
ADC Documented	Mar 3rd, 2022	Never	207	VeriLog	-
UART messages added to Pick and Place+e	Mar 3rd, 2022	Never	193	VeriLog	-
Untitled	Mar 3rd, 2022	Never	178	VeriLog	-
Electromagnet enabled LSA	Mar 1st, 2022	Never	231	VeriLog	-
SM Path+Dep 1.2	Mar 1st, 2022	Never	194	VeriLog	-
Path Traversal+Deposition SM	Feb 28th, 2022	Never	206	VeriLog	-
SM Path Traversal 1.1	Feb 28th, 2022	Never	200	VeriLog	-
Path Traversal SM	Feb 27th, 2022	Never	206	VeriLog	-
Dijkstra Sep	Feb 11th, 2022	Never	257	VeriLog	-
Dijkstra_only	Feb 11th, 2022	Never	175	VeriLog	-
LSA Backup	Feb 10th, 2022	Never	196	None	-
LSA Hardcoded	Feb 10th, 2022	Never	195	VeriLog	-
LSA Hardcoded TB	Feb 10th, 2022	Never	198	VeriLog	-
Hardcoded LSA	Feb 10th, 2022	Never	205	VeriLog	-
Untitled	Feb 9th, 2022	Never	191	VeriLog	-
Untitled	Feb 9th, 2022	Never	186	VeriLog	-
LSA+Dijkstra 2.0	Feb 9th, 2022	Never	199	VeriLog	-
Dijkstra+LSA	Feb 8th, 2022	Never	187	VeriLog	-
Dijkstra Reference	Feb 7th, 2022	Never	193	VeriLog	-
Dijkstra tb	Feb 6th, 2022	Never	189	VeriLog	-
Dijkstra	Feb 6th, 2022	Never	189	VeriLog	-
Dijkstra without input data	Feb 5th, 2022	Never	184	VeriLog	-
Dijkstra without input data	Feb 5th, 2022	Never	177	VeriLog	-
Untitled	Feb 5th, 2022	Never	184	VeriLog	-
Dijkstra rough	Feb 4th, 2022	Never	189	VeriLog	-
Untitled	Feb 4th, 2022	Never	175	VeriLog	-
Untitled	Feb 4th, 2022	Never	180	C++	-
Untitled	Feb 4th, 2022	Never	168	VeriLog	-
LED	Feb 1st, 2022	Never	173	VeriLog	-
LED	Feb 1st, 2022	Never	176	VeriLog	-
LED	Feb 1st, 2022	Never	154	None	-
LED_tb	Feb 1st, 2022	Never	171	VeriLog	-
Untitled	Jan 31st, 2022	Never	169	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	181	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	155	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	189	VeriLog	-
Untitled	Jan 31st, 2022	Never	156	None	-
Documented LSA	Jan 31st, 2022	Never	183	VeriLog	-