Sidsh's Pastebin

921 29,596 0 2 years ago

Name / Title	Added	Expires	Hits	Syntax
Untitled	Dec 4th, 2024	Never	3,419	SystemVerilog	-
Untitled	Dec 1st, 2024	Never	20	None	-
function cache rajni	Dec 1st, 2024	Never	118	SystemVerilog	-
Untitled	Nov 8th, 2024	Never	26	None	-
Untitled	Nov 2nd, 2022	Never	374	None	-
Reporting system	Oct 29th, 2022	Never	1,350	SystemVerilog	-
sequencer.sv	Oct 29th, 2022	Never	1,363	SystemVerilog	-
monitor.sv	Oct 29th, 2022	Never	1,423	SystemVerilog	-
driver.sv	Oct 29th, 2022	Never	1,405	SystemVerilog	-
interface.sv	Oct 29th, 2022	Never	1,296	SystemVerilog	-
sequence.sv	Oct 29th, 2022	Never	1,501	SystemVerilog	-
sequence_item.sv	Oct 29th, 2022	Never	1,448	SystemVerilog	-
agent.sv	Oct 29th, 2022	Never	1,314	SystemVerilog	-
env.sv	Oct 29th, 2022	Never	1,344	SystemVerilog	-
test.sv	Oct 29th, 2022	Never	1,303	SystemVerilog	-
top.sv	Oct 29th, 2022	Never	1,253	SystemVerilog	-
Haskell blinker.	Jun 26th, 2022	Never	431	Haskell	-
Haskell Blinker	Jun 26th, 2022	Never	180	None	-
Haskell Blinker	Jun 26th, 2022	Never	391	Haskell	-
Blinker Haskell;	Jun 26th, 2022	Never	299	Haskell	-
WB_pwmaudiocontroller	Apr 10th, 2022	Never	832	SystemVerilog	-
Counter	Mar 25th, 2022	Never	161	None	-
LSA Documented 2.0	Mar 3rd, 2022	Never	321	VeriLog	-
LED Documented (sec*) 2.0	Mar 3rd, 2022	Never	162	None	-
ADC Documented 2.0	Mar 3rd, 2022	Never	338	VeriLog	-
LSA Documented 1.1	Mar 3rd, 2022	Never	342	VeriLog	-
LED Documented (sec*)	Mar 3rd, 2022	Never	321	VeriLog	-
ADC Documented	Mar 3rd, 2022	Never	200	VeriLog	-
UART messages added to Pick and Place+e	Mar 3rd, 2022	Never	187	VeriLog	-
Untitled	Mar 3rd, 2022	Never	171	VeriLog	-
Electromagnet enabled LSA	Mar 1st, 2022	Never	223	VeriLog	-
SM Path+Dep 1.2	Mar 1st, 2022	Never	190	VeriLog	-
Path Traversal+Deposition SM	Feb 28th, 2022	Never	202	VeriLog	-
SM Path Traversal 1.1	Feb 28th, 2022	Never	193	VeriLog	-
Path Traversal SM	Feb 27th, 2022	Never	198	VeriLog	-
Dijkstra Sep	Feb 11th, 2022	Never	247	VeriLog	-
Dijkstra_only	Feb 11th, 2022	Never	170	VeriLog	-
LSA Backup	Feb 10th, 2022	Never	192	None	-
LSA Hardcoded	Feb 10th, 2022	Never	191	VeriLog	-
LSA Hardcoded TB	Feb 10th, 2022	Never	191	VeriLog	-
Hardcoded LSA	Feb 10th, 2022	Never	200	VeriLog	-
Untitled	Feb 9th, 2022	Never	185	VeriLog	-
Untitled	Feb 9th, 2022	Never	181	VeriLog	-
LSA+Dijkstra 2.0	Feb 9th, 2022	Never	191	VeriLog	-
Dijkstra+LSA	Feb 8th, 2022	Never	180	VeriLog	-
Dijkstra Reference	Feb 7th, 2022	Never	185	VeriLog	-
Dijkstra tb	Feb 6th, 2022	Never	183	VeriLog	-
Dijkstra	Feb 6th, 2022	Never	185	VeriLog	-
Dijkstra without input data	Feb 5th, 2022	Never	179	VeriLog	-
Dijkstra without input data	Feb 5th, 2022	Never	172	VeriLog	-
Untitled	Feb 5th, 2022	Never	180	VeriLog	-
Dijkstra rough	Feb 4th, 2022	Never	184	VeriLog	-
Untitled	Feb 4th, 2022	Never	171	VeriLog	-
Untitled	Feb 4th, 2022	Never	174	C++	-
Untitled	Feb 4th, 2022	Never	162	VeriLog	-
LED	Feb 1st, 2022	Never	167	VeriLog	-
LED	Feb 1st, 2022	Never	171	VeriLog	-
LED	Feb 1st, 2022	Never	149	None	-
LED_tb	Feb 1st, 2022	Never	164	VeriLog	-
Untitled	Jan 31st, 2022	Never	164	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	175	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	151	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	182	VeriLog	-
Untitled	Jan 31st, 2022	Never	148	None	-
Documented LSA	Jan 31st, 2022	Never	177	VeriLog	-