Sidsh's Pastebin

978 34,026 0 3 years ago

Name / Title	Added	Expires	Hits	Syntax
Untitled	Dec 4th, 2024	Never	6,012	SystemVerilog	-
Untitled	Dec 1st, 2024	Never	40	None	-
function cache rajni	Dec 1st, 2024	Never	282	SystemVerilog	-
Untitled	Nov 8th, 2024	Never	48	None	-
Untitled	Nov 2nd, 2022	Never	395	None	-
Reporting system	Oct 29th, 2022	Never	1,374	SystemVerilog	-
sequencer.sv	Oct 29th, 2022	Never	1,388	SystemVerilog	-
monitor.sv	Oct 29th, 2022	Never	1,470	SystemVerilog	-
driver.sv	Oct 29th, 2022	Never	1,456	SystemVerilog	-
interface.sv	Oct 29th, 2022	Never	1,329	SystemVerilog	-
sequence.sv	Oct 29th, 2022	Never	1,550	SystemVerilog	-
sequence_item.sv	Oct 29th, 2022	Never	1,508	SystemVerilog	-
agent.sv	Oct 29th, 2022	Never	1,359	SystemVerilog	-
env.sv	Oct 29th, 2022	Never	1,397	SystemVerilog	-
test.sv	Oct 29th, 2022	Never	1,327	SystemVerilog	-
top.sv	Oct 29th, 2022	Never	1,274	SystemVerilog	-
Haskell blinker.	Jun 26th, 2022	Never	452	Haskell	-
Haskell Blinker	Jun 26th, 2022	Never	201	None	-
Haskell Blinker	Jun 26th, 2022	Never	413	Haskell	-
Blinker Haskell;	Jun 26th, 2022	Never	331	Haskell	-
WB_pwmaudiocontroller	Apr 10th, 2022	Never	875	SystemVerilog	-
Counter	Mar 25th, 2022	Never	187	None	-
LSA Documented 2.0	Mar 3rd, 2022	Never	350	VeriLog	-
LED Documented (sec*) 2.0	Mar 3rd, 2022	Never	186	None	-
ADC Documented 2.0	Mar 3rd, 2022	Never	360	VeriLog	-
LSA Documented 1.1	Mar 3rd, 2022	Never	370	VeriLog	-
LED Documented (sec*)	Mar 3rd, 2022	Never	344	VeriLog	-
ADC Documented	Mar 3rd, 2022	Never	224	VeriLog	-
UART messages added to Pick and Place+e	Mar 3rd, 2022	Never	210	VeriLog	-
Untitled	Mar 3rd, 2022	Never	202	VeriLog	-
Electromagnet enabled LSA	Mar 1st, 2022	Never	250	VeriLog	-
SM Path+Dep 1.2	Mar 1st, 2022	Never	204	VeriLog	-
Path Traversal+Deposition SM	Feb 28th, 2022	Never	217	VeriLog	-
SM Path Traversal 1.1	Feb 28th, 2022	Never	215	VeriLog	-
Path Traversal SM	Feb 27th, 2022	Never	225	VeriLog	-
Dijkstra Sep	Feb 11th, 2022	Never	275	VeriLog	-
Dijkstra_only	Feb 11th, 2022	Never	191	VeriLog	-
LSA Backup	Feb 10th, 2022	Never	212	None	-
LSA Hardcoded	Feb 10th, 2022	Never	213	VeriLog	-
LSA Hardcoded TB	Feb 10th, 2022	Never	211	VeriLog	-
Hardcoded LSA	Feb 10th, 2022	Never	228	VeriLog	-
Untitled	Feb 9th, 2022	Never	208	VeriLog	-
Untitled	Feb 9th, 2022	Never	202	VeriLog	-
LSA+Dijkstra 2.0	Feb 9th, 2022	Never	218	VeriLog	-
Dijkstra+LSA	Feb 8th, 2022	Never	200	VeriLog	-
Dijkstra Reference	Feb 7th, 2022	Never	213	VeriLog	-
Dijkstra tb	Feb 6th, 2022	Never	203	VeriLog	-
Dijkstra	Feb 6th, 2022	Never	209	VeriLog	-
Dijkstra without input data	Feb 5th, 2022	Never	195	VeriLog	-
Dijkstra without input data	Feb 5th, 2022	Never	192	VeriLog	-
Untitled	Feb 5th, 2022	Never	201	VeriLog	-
Dijkstra rough	Feb 4th, 2022	Never	200	VeriLog	-
Untitled	Feb 4th, 2022	Never	187	VeriLog	-
Untitled	Feb 4th, 2022	Never	197	C++	-
Untitled	Feb 4th, 2022	Never	182	VeriLog	-
LED	Feb 1st, 2022	Never	188	VeriLog	-
LED	Feb 1st, 2022	Never	186	VeriLog	-
LED	Feb 1st, 2022	Never	167	None	-
LED_tb	Feb 1st, 2022	Never	192	VeriLog	-
Untitled	Jan 31st, 2022	Never	191	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	201	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	173	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	206	VeriLog	-
Untitled	Jan 31st, 2022	Never	167	None	-
Documented LSA	Jan 31st, 2022	Never	197	VeriLog	-