Sidsh's Pastebin

893 25,480 0 2 years ago

Name / Title	Added	Expires	Hits	Syntax
Untitled	Dec 4th, 2024	Never	31	SystemVerilog	-
Untitled	Dec 1st, 2024	Never	14	None	-
function cache rajni	Dec 1st, 2024	Never	23	SystemVerilog	-
Untitled	Nov 8th, 2024	Never	21	None	-
Untitled	Nov 2nd, 2022	Never	366	None	-
Reporting system	Oct 29th, 2022	Never	1,340	SystemVerilog	-
sequencer.sv	Oct 29th, 2022	Never	1,346	SystemVerilog	-
monitor.sv	Oct 29th, 2022	Never	1,397	SystemVerilog	-
driver.sv	Oct 29th, 2022	Never	1,374	SystemVerilog	-
interface.sv	Oct 29th, 2022	Never	1,291	SystemVerilog	-
sequence.sv	Oct 29th, 2022	Never	1,463	SystemVerilog	-
sequence_item.sv	Oct 29th, 2022	Never	1,423	SystemVerilog	-
agent.sv	Oct 29th, 2022	Never	1,286	SystemVerilog	-
env.sv	Oct 29th, 2022	Never	1,311	SystemVerilog	-
test.sv	Oct 29th, 2022	Never	1,293	SystemVerilog	-
top.sv	Oct 29th, 2022	Never	1,239	SystemVerilog	-
Haskell blinker.	Jun 26th, 2022	Never	423	Haskell	-
Haskell Blinker	Jun 26th, 2022	Never	175	None	-
Haskell Blinker	Jun 26th, 2022	Never	385	Haskell	-
Blinker Haskell;	Jun 26th, 2022	Never	286	Haskell	-
WB_pwmaudiocontroller	Apr 10th, 2022	Never	805	SystemVerilog	-
Counter	Mar 25th, 2022	Never	155	None	-
LSA Documented 2.0	Mar 3rd, 2022	Never	317	VeriLog	-
LED Documented (sec*) 2.0	Mar 3rd, 2022	Never	155	None	-
ADC Documented 2.0	Mar 3rd, 2022	Never	333	VeriLog	-
LSA Documented 1.1	Mar 3rd, 2022	Never	328	VeriLog	-
LED Documented (sec*)	Mar 3rd, 2022	Never	315	VeriLog	-
ADC Documented	Mar 3rd, 2022	Never	192	VeriLog	-
UART messages added to Pick and Place+e	Mar 3rd, 2022	Never	178	VeriLog	-
Untitled	Mar 3rd, 2022	Never	161	VeriLog	-
Electromagnet enabled LSA	Mar 1st, 2022	Never	214	VeriLog	-
SM Path+Dep 1.2	Mar 1st, 2022	Never	185	VeriLog	-
Path Traversal+Deposition SM	Feb 28th, 2022	Never	194	VeriLog	-
SM Path Traversal 1.1	Feb 28th, 2022	Never	183	VeriLog	-
Path Traversal SM	Feb 27th, 2022	Never	186	VeriLog	-
Dijkstra Sep	Feb 11th, 2022	Never	230	VeriLog	-
Dijkstra_only	Feb 11th, 2022	Never	164	VeriLog	-
LSA Backup	Feb 10th, 2022	Never	184	None	-
LSA Hardcoded	Feb 10th, 2022	Never	183	VeriLog	-
LSA Hardcoded TB	Feb 10th, 2022	Never	185	VeriLog	-
Hardcoded LSA	Feb 10th, 2022	Never	184	VeriLog	-
Untitled	Feb 9th, 2022	Never	173	VeriLog	-
Untitled	Feb 9th, 2022	Never	171	VeriLog	-
LSA+Dijkstra 2.0	Feb 9th, 2022	Never	178	VeriLog	-
Dijkstra+LSA	Feb 8th, 2022	Never	171	VeriLog	-
Dijkstra Reference	Feb 7th, 2022	Never	177	VeriLog	-
Dijkstra tb	Feb 6th, 2022	Never	176	VeriLog	-
Dijkstra	Feb 6th, 2022	Never	179	VeriLog	-
Dijkstra without input data	Feb 5th, 2022	Never	173	VeriLog	-
Dijkstra without input data	Feb 5th, 2022	Never	165	VeriLog	-
Untitled	Feb 5th, 2022	Never	173	VeriLog	-
Dijkstra rough	Feb 4th, 2022	Never	175	VeriLog	-
Untitled	Feb 4th, 2022	Never	163	VeriLog	-
Untitled	Feb 4th, 2022	Never	167	C++	-
Untitled	Feb 4th, 2022	Never	156	VeriLog	-
LED	Feb 1st, 2022	Never	159	VeriLog	-
LED	Feb 1st, 2022	Never	165	VeriLog	-
LED	Feb 1st, 2022	Never	143	None	-
LED_tb	Feb 1st, 2022	Never	158	VeriLog	-
Untitled	Jan 31st, 2022	Never	158	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	166	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	144	VeriLog	-
Stop logic LSA	Jan 31st, 2022	Never	166	VeriLog	-
Untitled	Jan 31st, 2022	Never	139	None	-
Documented LSA	Jan 31st, 2022	Never	167	VeriLog	-