# Start time: 22:59:05 on Nov 07,2024
# ** Note: (vsim-3812) Design is being optimized...
# ** Error (suppressible): /u/patilsid/ECE508-verilog_wksp/hw2_releaseR0/problem2/tb_findMax.sv(34): (vopt-7063) Failed to find 'FSM' in hierarchical name 'DUT.FSM.st'.
#         Region: tb_findMax
# ** Error (suppressible): /u/patilsid/ECE508-verilog_wksp/hw2_releaseR0/problem2/tb_findMax.sv(34): (vopt-7063) Failed to find 'FSM' in hierarchical name 'DUT.FSM.ns'.
#         Region: tb_findMax
# Optimization failed
# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=2, Warnings=0.