LED_tb

`timescale 1ns/1ns

module LED_tb;
//inputs
reg[2:0] hl;
reg hl1;
reg [2:0] id;
reg clk;

//output
wire r1;
wire g2;
wire b3;

//instantiate unit under test

LED uut (
.hl(hl) ,
.hl1(hl1),
.id(id),
.clk_50(clk),
.r1(r1),
.g2(g2),
.b3(b3)
);

initial begin
     // Initialize Inputs
$monitor(" ",hl," ",hl1," ",id," ",r1," ", g2," ",b3);

 $dumpfile("LED.vcd");
    $dumpvars;
    $dumpvars(6,hl,hl1,id,r1,g2,b3);

  end
always begin

    clk = 0; #10;
    clk = 1; #10;

end
initial begin
 id = 1;hl = 0;
 end
always@(posedge clk)
begin
id[2:0] = 3'b001;hl = 0; #10000;
id[2:0] = 3'b010; hl = 1; #10000;
id[2:0] = 3'b011; hl =2 ;#10000;
id[2:0] = 3'b001;hl = 3; #10000;
id[2:0] = 3'b010; hl = 4; #10000;
id[2:0] = 3'b011; hl =5 ;#10000;
id[2:0] = 3'b001;hl = 6; #10000;
id[2:0] = 3'b010; hl = 7; #10000;
id[2:0] = 3'b011; hl = 8;#10000;
end

endmodule