Counter

// Code your design here
module counter (clk,data,reset,count)
  input data;
  input clk;
  input reset;
  output reg [4:0] count;

  reg flag =0;

  always@(posedge clk)
    begin
      if (reset ==1)
        begin
          count<=0;
        end
      if (data ==1 && flag ==1)
        begin
          count=count +1;
          flag=0;
        end
      if (data==0)
        begin
          flag<=1;
        end
    end
endmodule