petrdynin

Petrdynin's Pastebin

19 527 0 1 year ago
Name / Title Added Expires Hits Comments Syntax  
MIK32+UART_RX+DMA Sep 17th, 2024 Never 51 0 C -
interrupt Feb 16th, 2024 Never 55 0 C -
Untitled Jan 21st, 2024 Never 100 0 SystemVerilog -
Lesson_6_task_03_row_testbench Jan 19th, 2024 Never 84 0 SystemVerilog -
CH32V307_SPI_HardNSS Jan 19th, 2024 Never 77 0 C -
Untitled Dec 5th, 2023 Never 86 0 SystemVerilog -
Untitled Dec 5th, 2023 Never 77 0 SystemVerilog -