MIK32+UART_RX+DMA

#define DMA_BUFFER_SIZE 16

typedef struct {
    uint16_t   ri, ct;
    uint8_t    buff[DMA_BUFFER_SIZE];
} FIFO;

volatile FIFO RxFifo_1;


void DMA_Initialize(void){

      PM->CLK_AHB_SET |= PM_CLOCK_AHB_DMA_M;

      DMA_CONFIG->CONFIG_STATUS  =  DMA_CONFIG_CLEAR_LOCAL_IRQ_M
                          //      |   DMA_CONFIG_CLEAR_GLOBAL_IRQ_M
                          //      |   DMA_CONFIG_CLEAR_ERROR_IRQ_M
                          //      |   DMA_CONFIG_GLOBAL_IRQ_ENA_M
                          //      |   DMA_CONFIG_ERROR_IRQ_ENA_M
                          //      |   DMA_CONFIG_CURRENT_VALUE_M
                                  ;

}


void DMA_Ch1_Initialize(void){

      DMA_CONFIG->CHANNELS[1].SRC = (uint32_t)&(UART_1->RXDATA);
      DMA_CONFIG->CHANNELS[1].DST = (uint32_t)RxFifo_1.buff;
      DMA_CONFIG->CHANNELS[1].LEN = DMA_BUFFER_SIZE-1;

      DMA_CONFIG->CHANNELS[1].CFG = DMA_CH_CFG_PRIOR_VERY_HIGH_M

                                |   DMA_CH_CFG_READ_MODE_PERIPHERY_M
                                |   DMA_CH_CFG_READ_NO_INCREMENT_M
                                |   DMA_CH_CFG_READ_SIZE_BYTE_M
                                |   0 << DMA_CH_CFG_READ_BURST_SIZE_S
                                |   DMA_CH_CFG_READ_REQUETS(1)
                                |   DMA_CH_CFG_READ_ACK_EN_M

                                |   DMA_CH_CFG_WRITE_MODE_MEMORY_M
                                |   DMA_CH_CFG_WRITE_INCREMENT_M
                                |   DMA_CH_CFG_WRITE_SIZE_BYTE_M
                                |   0 << DMA_CH_CFG_WRITE_BURST_SIZE_S
                                |   DMA_CH_CFG_IRQ_EN_M

                                |  DMA_CH_CFG_ENABLE_M
                                ;
}

/*****************  часть обработчика прерывания от DMA *****************************/

       if ( EPIC->RAW_STATUS & (1<<EPIC_DMA_INDEX)){
           EPIC->CLEAR = (1<<EPIC_DMA_INDEX);

           if(DMA_CONFIG->CONFIG_STATUS & DMA_CONFIG_CLEAR_LOCAL_IRQ(1)<<4){

               DMA_CONFIG->CONFIG_STATUS = DMA_CONFIG_CLEAR_LOCAL_IRQ(1)
                                         | DMA_CONFIG_CURRENT_VALUE_M
                                         ;
               DMA_CONFIG->CHANNELS[1].CFG |= DMA_CH_CFG_ENABLE_M;
           }

           DMA_CONFIG->CONFIG_STATUS &= ~DMA_CONFIG_CURRENT_VALUE_M;

        }
/*************************************************************************************/



uint16_t uart1_test(void) {

    static uint16_t old_ct = 0;
    uint16_t new_ct = DMA_CONFIG->CHANNELS[1].LEN;
    uint16_t rx_ct = 0;


    if (new_ct >= old_ct) {
        rx_ct = new_ct - old_ct;
    } else {
        rx_ct = (DMA_BUFFER_SIZE - old_ct) + new_ct;
    }

    old_ct = new_ct;
    RxFifo_1.ct += rx_ct;
    if (RxFifo_1.ct > DMA_BUFFER_SIZE) {
        RxFifo_1.ct = DMA_BUFFER_SIZE;
    }

    return RxFifo_1.ct;
}


uint16_t uart1_getc (void)
{
    uint8_t  d;
    uint16_t i;

    i = RxFifo_1.ri;
    d = RxFifo_1.buff[i++];
    RxFifo_1.ri = i % DMA_BUFFER_SIZE;
    RxFifo_1.ct--;

    return d;
}



    /*****************  крутится в цикле *****************************/

    while (1)
        {

            if(uart1_test()){
                uart1_putc(uart1_getc());  // эхо
            }

            // задача 2

            // задача 3


            // задача N

        }