Mode

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-- Company:
-- Engineer:
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-- Create Date: 17.11.2023 20:47:10
-- Design Name:
-- Module Name: Mode - archi
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
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-- Dependencies:
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-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Mode is Port (
    Pause_Rqt,Endframe,Lost,No_Brick,Clk25,Reset : in std_logic;
    Game_lost,Brick_Win,Pause : out std_logic );

end Mode;

architecture archi of Mode is

signal Fin_Tempo_Pause, RAZ_Tempo_Pause , Update_Tempo_Pause , Load_Timer_Lost , Update_Timer_Lost : std_logic;
signal Timer_Cpt_Tempo : std_logic_vector (9 downto 0);
signal Timer_Lost_cpt : std_logic_vector(5 downto 0);


begin

--Instanciation Tempo_Pause
Tempo : entity work.Tempo
        port map(Clk25,Reset,RAZ_Tempo_Pause,Update_Tempo_Pause,Timer_Cpt_Tempo,Fin_Tempo_Pause);

--Instanciation Timer_Lost
Timer_Lost : entity work.Timer_Lost
             port map(Clk25,Reset,Load_Timer_Lost,Update_Timer_Lost,Timer_Lost_cpt,Game_lost);

--Instanciation MAE MODE
MAE_Mode : entity work.MAE_Mode
       port map(Clk25,Reset,Pause_Rqt,Endframe,Lost,No_brick,Fin_Tempo_Pause,Timer_Lost_cpt,Brick_Win,Pause,RAZ_Tempo_Pause,Update_Tempo_Pause,Load_Timer_Lost,Update_Timer_Lost);

end archi;