module fsm(output reg out, input in, clk, reset_n);
reg [2:0] state, next_state;

// partea secvențială
always @(posedge clk) begin
    if (reset_n == 0) state <= 0;
    else state <= next_state;
end

// partea combinationala
always @(*) begin
    out = 0;
    case (state)
        0:   if (in == 0) begin
                 next_state = 1;
                 out = 1;
             end
             else next_state = 2;
        1:   if (in == 0) begin
                 next_state = 3;
                 out = 1;
             end
             else next_state = 4;
    ...
    endcase
end
endmodule