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aidanozo

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Oct 27th, 2024
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  1. module debouncer(
  2.         clk,
  3.         in,
  4.         out
  5.     );
  6.  
  7. parameter counter_width = 20;
  8. parameter counter_value = 1000000;
  9.  
  10. input           clk;
  11. input           in;
  12. output reg  out = 0;
  13.  
  14. reg prev_in = 0;
  15. reg[counter_width-1 : 0] counter = 0;
  16.  
  17. always @(posedge clk) begin
  18.     if(counter == counter_value)
  19.         out <= prev_in;
  20.        
  21.     if(in != prev_in)
  22.         counter <= 0;
  23.     else
  24.         counter <= counter + 1;
  25.    
  26.     prev_in <= in;
  27. end
  28.  
  29. endmodule
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