--------------HALF ADDER---------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity HalfAdder is
  Port ( A, B : in STD_LOGIC;
         Sum, Carry : out STD_LOGIC);
end HalfAdder;

architecture Behavioral of HalfAdder is
begin
  process(A, B)
  begin
    Sum <= A XOR B;    -- XOR gives the sum bit
    Carry <= A AND B;  -- AND gives the carry bit
  end process;
end Behavioral;




------------------ALU--------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity FourBitALU is
  Port ( A, B : in STD_LOGIC_VECTOR(3 downto 0);
         opcode : in STD_LOGIC_VECTOR(2 downto 0);
         result : out STD_LOGIC_VECTOR(3 downto 0));
end FourBitALU;

architecture Behavioral of FourBitALU is
  signal temp_result : STD_LOGIC_VECTOR(4 downto 0); -- To handle overflow
begin

  process(A, B, opcode)
  begin
    case opcode is
      when "000" => -- ADD
        temp_result <= ('0' & A) + ('0' & B);
      when "001" => -- SUBTRACT
        temp_result <= ('0' & A) - ('0' & B);
      when "010" => -- AND
        temp_result <= A AND B;
      when "011" => -- OR
        temp_result <= A OR B;
      when "100" => -- XOR
        temp_result <= A XOR B;
      when "101" => -- NAND
        temp_result <= A NAND B;
      when "110" => -- NOR
        temp_result <= A NOR B;
      when "111" => -- NOT
        temp_result <= not A;
      when others =>
        temp_result <= (others => '0');
    end case;

    result <= temp_result(3 downto 0); -- Extract the 4-bit result
  end process;

end Behavioral;






-------------------COUNTER--------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity UpDownCounter is
  Port ( clk : in STD_LOGIC;
         rst : in STD_LOGIC;
         up_down : in STD_LOGIC;
         count : out STD_LOGIC_VECTOR(3 downto 0));
end UpDownCounter;

architecture Behavioral of UpDownCounter is
  signal counter : STD_LOGIC_VECTOR(3 downto 0) := "0000";
begin

  process(clk, rst)
  begin
    if rst = '1' then
      counter <= "0000"; -- Reset the counter to 0
    elsif rising_edge(clk) then
      if up_down = '1' then
        -- Up counter
        counter <= counter + 1;
      else
        -- Down counter
        counter <= counter - 1;
      end if;
    end if;
  end process;

  count <= counter;

end Behavioral;






--------------Seven Segment------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity SevenSegmentDisplay is
  Port ( clk : in STD_LOGIC;
         rst : in STD_LOGIC;
         seg : out STD_LOGIC_VECTOR(6 downto 0);
         anode : out STD_LOGIC);
end SevenSegmentDisplay;

architecture Behavioral of SevenSegmentDisplay is
  signal counter : INTEGER range 0 to 9 := 0;
  signal display_pattern : STD_LOGIC_VECTOR(6 downto 0);

begin

  process(clk, rst)
  begin
    if rst = '1' then
      counter <= 0;
      display_pattern <= "0000000"; -- Reset to display pattern for 0
    elsif rising_edge(clk) then
      if counter < 9 then
        counter <= counter + 1;
      else
        counter <= 0;
      end if;

      case counter is
        when 0 => display_pattern <= "0000001"; -- 0
        when 1 => display_pattern <= "1001111"; -- 1
        when 2 => display_pattern <= "0010010"; -- 2
        when 3 => display_pattern <= "0000110"; -- 3
        when 4 => display_pattern <= "1001100"; -- 4
        when 5 => display_pattern <= "0100100"; -- 5
        when 6 => display_pattern <= "0100000"; -- 6
        when 7 => display_pattern <= "0001111"; -- 7
        when 8 => display_pattern <= "0000000"; -- 8
        when 9 => display_pattern <= "0000100"; -- 9
        when others => display_pattern <= "1111111"; -- All segments off for invalid input
      end case;
    end if;
  end process;

  seg <= display_pattern;
  anode <= '1'; -- Anode control signal (common anode display)

end Behavioral;






-----------------FIFO-------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity FourBitFIFO is
  Port ( clk : in STD_LOGIC;
         rst : in STD_LOGIC;
         wr_en : in STD_LOGIC;
         rd_en : in STD_LOGIC;
         data_in : in STD_LOGIC_VECTOR(3 downto 0);
         data_out : out STD_LOGIC_VECTOR(3 downto 0);
         empty : inout STD_LOGIC;
         full : inout STD_LOGIC);
end FourBitFIFO;

architecture Behavioral of FourBitFIFO is
  type MemoryArray is array (0 to 7) of STD_LOGIC_VECTOR(3 downto 0);
  signal fifo_memory : MemoryArray := (others => "0000");
  signal read_ptr, write_ptr : integer range 0 to 7 := 0;
begin

  process(clk, rst)
  begin
    if rst = '1' then
      read_ptr <= 0;
      write_ptr <= 0;
      fifo_memory <= (others => "0000");
    elsif rising_edge(clk) then
      -- Write operation
      if wr_en = '1' and not full = '1' then
        fifo_memory(write_ptr) <= data_in;
        write_ptr <= write_ptr + 1;
      end if;

      -- Read operation
      if rd_en = '1' and not empty = '1' then
        data_out <= fifo_memory(read_ptr);
        read_ptr <= read_ptr + 1;
      end if;
    end if;
  end process;

  empty <= '1' when read_ptr = write_ptr else '0';
  full <= '1' when ((write_ptr + 1) mod 8) = read_ptr else '0';

end Behavioral;





-----------------UNIVERSAL SHIFT REGISTER-----------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity UniversalShiftRegister is
  Port ( clk : in STD_LOGIC;
         load : in STD_LOGIC;
         shift_left : in STD_LOGIC;
         shift_right : in STD_LOGIC;
         data_in : in STD_LOGIC_VECTOR(3 downto 0);
         data_out : out STD_LOGIC_VECTOR(3 downto 0));
end UniversalShiftRegister;

architecture Behavioral of UniversalShiftRegister is
  signal shift_register : STD_LOGIC_VECTOR(3 downto 0) := "0000";
begin

  process(clk)
  begin
    if rising_edge(clk) then
      if load = '1' then
        shift_register <= data_in; -- Parallel load
      else
        if shift_left = '1' then
          shift_register <= '0' & shift_register(3 downto 1); -- Left shift
        elsif shift_right = '1' then
          shift_register <= shift_register(2 downto 0) & '0'; -- Right shift
        end if;
      end if;
    end if;
  end process;

  data_out <= shift_register;

end Behavioral;