library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- warning: this file will not be saved if:
--     * following entity block contains any syntactic errors (e.g. port list isn't separated with ; character)
--     * following entity name and current file name differ (e.g. if file is named mux41 then entity must also be named mux41 and vice versa)
ENTITY funkcija IS port(
    input : in std_logic_vector (0 to 2);
    output : out std_logic_vector (5 downto 0));
END funkcija;

ARCHITECTURE arch OF funkcija IS
    signal a,b,c: std_logic;
BEGIN
    a <= input(0);
    b <= input(1);
    c <= input(2);

    output(0) <= a;
    output(1) <= (not a and not b and c) or (not a and b and not c) or (a and b and c) or (a and not b and not c);
    output(2) <= not c;
    output(3) <= (not a and not b and not c) or (not a and c) or a;
    output(4) <= not a or (a and c);
    output(5) <= b and c;

END arch;