8 Cores

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity CPU is
    Port ( CLK : in  STD_LOGIC;
           RST : in  STD_LOGIC;
           Instr : in  STD_LOGIC_VECTOR (7 downto 0);
           Result : out  STD_LOGIC_VECTOR (7 downto 0));
end CPU;

architecture Behavioral of CPU is
    signal A, B : STD_LOGIC_VECTOR (7 downto 0);
    signal ALU_Result : STD_LOGIC_VECTOR (7 downto 0);
    signal ALU_Op : STD_LOGIC_VECTOR (2 downto 0);
begin
    process(CLK, RST)
    begin
        if RST = '1' then
            A <= (others => '0');
            B <= (others => '0');
            ALU_Op <= "000";
        elsif rising_edge(CLK) then
            -- Simulando una operación simple
            A <= Instr(7 downto 4);
            B <= Instr(3 downto 0);
            ALU_Op <= Instr(2 downto 0);
        end if;
    end process;

    -- ALU simple
    process(ALU_Op, A, B)
    begin
        case ALU_Op is
            when "000" => ALU_Result <= A + B;
            when "001" => ALU_Result <= A - B;
            when "010" => ALU_Result <= A and B;
            when "011" => ALU_Result <= A or B;
            when others => ALU_Result <= (others => '0');
        end case;
    end process;

    Result <= ALU_Result;

end Behavioral;