I2S_testbench

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02/25/2024 06:55:40 PM
// Design Name:
// Module Name: Testbench
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////



module Testbench;

reg clk_system;
reg clk_I2S;

initial
begin
    clk_system = 1'b0;
    clk_I2S = 1'b0;
end

always
begin
    clk_system = ~clk_system;
    #1; //ns -> f = 1MHz
end

always
begin
    clk_I2S = ~clk_I2S;
    #10_416.667; //ns -> f = 96kHz
end

reg rstn;
initial
begin
    rstn = 1'b0;
    #50_000;
    rstn = 1'b1;
end

reg en;
initial
begin
    en = 1'b1;
    #3_000_000;
    en = 1'b0;
end

wire lrclk;
wire bclk;
wire sd;

wire [23:0] adc_data;
wire adc_valid_l;
wire adc_valid_r;

I2S_receiver receiver
(
    .clk(clk_system),
    .rstn(rstn),
    .en(en),
    .lrclk(lrclk),
    .bclk(bclk),
    .sdi(sd),

    .adc_data(adc_data),
    .adc_valid_l(adc_valid_l),
    .adc_valid_r(adc_valid_r)
);

I2S_transmitter transmitter
(
    .clk(clk_I2S),
    .rstn(rstn),
    .lrclk(lrclk),
    .bclk(bclk),
    .sdo(sd)
);

endmodule