edge_detector_fsm

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity edge_detector is
  port (
    rst_i    : in  std_logic;
    clk_i    : in  std_logic;
    strobe_i : in  std_logic;
    p1_o     : out std_logic;
    p2_o     : out std_logic;
    p3_o     : out std_logic);
end entity edge_detector;

architecture rtl of edge_detector is
    type FSM_L is (ZERO, EDGE, ONE);
    type FSM_M is (ZERO, ONE);
    type FSM_R is (ZERO, DELAY, ONE);

    signal cur_state_l_s: FSM_L := ZERO;
    signal nxt_state_l_s: FSM_L := ZERO;

    signal cur_state_m_s: FSM_M := ZERO;
    signal nxt_state_m_s: FSM_M := ZERO;

    signal cur_state_r_s: FSM_R := ZERO;
    signal nxt_state_r_s: FSM_R := ZERO;

begin  -- architecture rtl
    transitions: process(cur_state_l_s, strobe_i) is
        begin
            case cur_state_l_s is
                when ZERO =>
                    nxt_state_l_s <= ZERO;
                    if strobe_i = '1' then
                        nxt_state_l_s <= EDGE;
                    end if;
                when EDGE =>
                    nxt_state_l_s <= ZERO;
                    if strobe_i = '1' then
                        nxt_state_l_s <= ONE;
                    end if;
                when ONE =>
                    nxt_state_l_s <= ZERO;
                    if strobe_i = '1' then
                        nxt_state_l_s <= ONE;
                    end if;
            end case;
        end process transitions;

    next_state_process: process(clk_i) is
    begin
        if rising_edge(clk_i) and clk_i = '1' then
            if rst_i = '1' then
                cur_state_l_s <= ZERO;
            else
                cur_state_l_s <= nxt_state_l_s;
            end if;
        end if;
    end process next_state_process;

    output_process: process(cur_state_l_s) is
    begin
        p1_o <= '0';
--        case cur_state_l_s is
--            when ZERO =>
--                p1_o <= '0';
--            when EDGE =>
--                p1_o <= '1';
--            when ONE =>
--                p1_o <= '0';
--        end case;
        if cur_state_l_s = EDGE then
            p1_o <= '1';
        end if;
    end process output_process;

--    p2_o <= '0';
--    p3_o <= '0';

    transitions_M: process(cur_state_m_s, strobe_i) is
    begin
        case cur_state_m_s is
            when ZERO =>
                nxt_state_m_s <= ZERO;
                if strobe_i = '1' then
                    nxt_state_m_s <= ONE;
                end if;
            when ONE =>
                nxt_state_m_s <= ZERO;
                if strobe_i = '1' then
                    nxt_state_m_s <= ONE;
                end if;
        end case;
    end process transitions_M;

    next_state_process_M: process(clk_i) is
    begin
        if rising_edge(clk_i) then
            if rst_i = '1' then
                cur_state_m_s <= ZERO;
            else
                cur_state_m_s <= nxt_state_m_s;
            end if;
        end if;
    end process next_state_process_M;

    output_logic_M: process(cur_state_m_s) is
    begin
        p2_o <= '0';
        if cur_state_m_s = ZERO and strobe_i = '1' then
            p2_o <= '1';
        end if;
    end process output_logic_M;

    transitions_R: process(cur_state_r_s, strobe_i) is
    begin
        case cur_state_r_s is
            when ZERO =>
                nxt_state_r_s <= ZERO;
                if strobe_i = '1' then
                    nxt_state_r_s <= DELAY;
                end if;
            when DELAY =>
                nxt_state_r_s <= ZERO;
                if strobe_i = '1' then
                    nxt_state_r_s <= ONE;
                end if;
            when ONE =>
                nxt_state_r_s <= ZERO;
                if strobe_i = '1' then
                    nxt_state_r_s <= ONE;
                end if;
        end case;
    end process transitions_R;

    next_state_process_R: process(clk_i) is
    begin
        if rising_edge(clk_i) then
            if rst_i = '1' then
                cur_state_r_s <= ZERO;
            else
                cur_state_r_s <= nxt_state_r_s;
            end if;
        end if;
    end process next_state_process_R;

    output_logic_R: process(cur_state_r_s) is
    begin
        p3_o <= '0';
        case cur_state_r_s is
            when ZERO =>
                if strobe_i = '1' then
                    p3_o <= '1';
                end if;
            when DELAY =>
                p3_o <= '1';
            when ONE => null;
        end case;
    end process output_logic_R;

end architecture rtl;