clk10

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ClkDivMC is
    Port (
        Clk100, Reset: in std_logic;
        Clk10: out std_logic
    );
end ClkDivMC;

architecture archi of ClkDivMC is
    signal cpt : std_logic_vector(3 downto 0) := "0000";
    signal ClkDiviseur : std_logic := '0';

begin
    process (Clk100, Reset)
    begin
        if Reset = '0' then
            cpt <= "0000";
            ClkDiviseur <= '0';
        elsif rising_edge(Clk100) then
            if cpt = 4 then
                cpt <= "0000";
                ClkDiviseur <= not ClkDiviseur;
            else
                cpt <= cpt + 1;
            end if;
        end if;
    end process;

    Clk10 <= ClkDivider;
end archi;