VHDL Counter Program Template

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity counter30 is
    Port ( enable, reset, clock : in STD_LOGIC;
           a0,b0,c0,d0,e0,f0,g0 : out STD_LOGIC;
           a1,b1,c1,d1,e1,f1,g1 : out STD_LOGIC);
end counter30;

architecture Behavioral of counter30 is

signal clk_count : natural range 0 to 10 := 0; -- Untuk clock
signal puluhan : STD_LOGIC_VECTOR (6 downto 0) := "1000000"; -- Untuk seven segment puluhan
signal satuan : STD_LOGIC_VECTOR (6 downto 0) := "1000000"; -- Untuk seven segment satuan
signal puluhan_count : integer range 0 to 3 := 0; -- Untuk counter puluhan 10, 20, 30
signal satuan_count : integer range 0 to 9 := 0; -- Untuk counter satuan dari 0 sampai 9
signal overall_count : integer range 0 to 30 := 0; -- Untuk counter internal 0 sampai 30, boleh dipake boleh engga

begin
-- SILAHKAN ISI DISINI


with satuan_count select
    satuan <= "1000000" when 0,
              "1111001" when 1,
              "0100100" when 2,
              "0110000" when 3,
              "0011001" when 4,
              "0010010" when 5,
              "0000010" when 6,
              "1111000" when 7,
              "0000000" when 8,
              "0010000" when 9;

with puluhan_count select
    puluhan <= "1000000" when 0,
               "1111001" when 1,
               "0100100" when 2,
               "0110000" when 3;

a0 <= satuan(0);
b0 <= satuan(1);
c0 <= satuan(2);
d0 <= satuan(3);
e0 <= satuan(4);
f0 <= satuan(5);
g0 <= satuan(6);

a1 <= puluhan(0);
b1 <= puluhan(1);
c1 <= puluhan(2);
d1 <= puluhan(3);
e1 <= puluhan(4);
f1 <= puluhan(5);
g1 <= puluhan(6);

end Behavioral;