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silver2row

Ideas...

Mar 9th, 2024
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VHDL 0.52 KB | None | 0 0
  1. -- FROM ALTERA and INTEL online...
  2.  
  3. LIBRARY IEEE;
  4. USE IEEE.STD_LOGIC_1164.ALL;
  5. USE WORK.filt_cmp.ALL;
  6.  
  7. ENTITY cmpl_sig IS
  8. PORT (a, b, sel : IN STD_LOGIC;
  9.     x, y, z : OUT STD_LOGIC);
  10. END ENTITY cmpl_sig;
  11.  
  12. ARCHITECTURE logic OF cmpl_sig IS
  13. BEGIN
  14.     -- Simple Signal Assign...
  15.     X <= (a AND NOT sel) OR (b AND sel);
  16.     -- Cond. Signal Assign...
  17.     Y <= A WHEN sel='0' ELSE
  18.         B;
  19.     -- Selected Signal Assignment
  20.     Z <= a WHEN '0';
  21.          B WHEN '1';
  22.          '0' WHEN OTHERS;
  23. END ARCHITECTURE logic;
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