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- --------------------------------------------------------------------------------
- -- Company:
- -- Engineer:
- --
- -- Create Date: 12:31:45 10/29/2023
- -- Design Name:
- -- Module Name: D:/Fppga/simulasi/fsmandcounter/counterTest.vhd
- -- Project Name: fsmandcounter
- -- Target Device:
- -- Tool versions:
- -- Description:
- --
- -- VHDL Test Bench Created by ISE for module: fsmCounter
- --
- -- Dependencies:
- --
- -- Revision:
- -- Revision 0.01 - File Created
- -- Additional Comments:
- --
- -- Notes:
- -- This testbench has been automatically generated using types std_logic and
- -- std_logic_vector for the ports of the unit under test. Xilinx recommends
- -- that these types always be used for the top-level I/O of a design in order
- -- to guarantee that the testbench will bind correctly to the post-implementation
- -- simulation model.
- --------------------------------------------------------------------------------
- LIBRARY ieee;
- USE ieee.std_logic_1164.ALL;
- -- Uncomment the following library declaration if using
- -- arithmetic functions with Signed or Unsigned values
- --USE ieee.numeric_std.ALL;
- ENTITY counterTest IS
- END counterTest;
- ARCHITECTURE behavior OF counterTest IS
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT fsmCounter
- PORT(
- clk : IN std_logic;
- pb1 : IN std_logic;
- pb2 : IN std_logic;
- led : OUT std_logic_vector(3 downto 0)
- );
- END COMPONENT;
- --Inputs
- signal clk : std_logic := '0';
- signal pb1 : std_logic := '0';
- signal pb2 : std_logic := '0';
- --Outputs
- signal led : std_logic_vector(3 downto 0);
- -- Clock period definitions
- constant clk_period : time := 10 ns;
- BEGIN
- -- Instantiate the Unit Under Test (UUT)
- uut: fsmCounter PORT MAP (
- clk => clk,
- pb1 => pb1,
- pb2 => pb2,
- led => led
- );
- -- Clock process definitions
- clk_process :process
- begin
- clk <= '0';
- wait for clk_period/2;
- clk <= '1';
- wait for clk_period/2;
- end process;
- -- Stimulus process
- stim_proc: process
- begin
- -- hold reset state for 100 ns.
- wait for 10 ns;
- -- wait for clk_period*10;
- -- insert stimulus here
- pb1 <= '1';
- wait for 15 ns;
- pb1 <= '0';
- wait for 15 ns;
- pb1 <= '1';
- wait for 15 ns;
- pb1 <= '0';
- wait for 15 ns;
- pb1 <= '1';
- wait for 15 ns;
- pb1 <= '0';
- wait for 15 ns;
- pb1 <= '1';
- wait for 15 ns;
- pb1 <= '0';
- wait for 15 ns;
- pb1 <= '1';
- wait for 15 ns;
- pb1 <= '0';
- wait for 15 ns;
- pb1 <= '1';
- wait for 15 ns;
- pb1 <= '0';
- wait for 15 ns;
- pb1 <= '1';
- wait for 15 ns;
- pb1 <= '0';
- wait for 15 ns;
- pb1 <= '1';
- wait for 15 ns;
- pb1 <= '0';
- wait for 15 ns;
- pb1 <= '1';
- wait for 15 ns;
- pb1 <= '0';
- wait for 15 ns;
- pb1 <= '1';
- wait for 15 ns;
- pb1 <= '0';
- wait for 15 ns;
- pb1 <= '1';
- wait for 15 ns;
- pb1 <= '0';
- wait for 15 ns;
- pb1 <= '1';
- wait for 15 ns;
- pb1 <= '0';
- wait for 15 ns;
- pb1 <= '1';
- wait for 15 ns;
- pb1 <= '0';
- wait for 15 ns;
- pb1 <= '1';
- wait for 15 ns;
- pb1 <= '0';
- wait for 15 ns;
- pb1 <= '1';
- wait for 15 ns;
- pb1 <= '0';
- wait for 45 ns;
- pb2 <= '1';
- wait for 15 ns;
- pb2 <= '0';
- wait for 45 ns;
- pb1 <= '1';
- wait for 15 ns;
- pb1 <= '0';
- wait for 15 ns;
- pb1 <= '1';
- wait for 15 ns;
- pb1 <= '0';
- wait for 15 ns;
- wait;
- end process;
- END;
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