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Aftaza

testBench-fsmCounter

Oct 29th, 2023
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VHDL 3.50 KB | Source Code | 0 0
  1. --------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date:   12:31:45 10/29/2023
  6. -- Design Name:  
  7. -- Module Name:   D:/Fppga/simulasi/fsmandcounter/counterTest.vhd
  8. -- Project Name:  fsmandcounter
  9. -- Target Device:  
  10. -- Tool versions:  
  11. -- Description:  
  12. --
  13. -- VHDL Test Bench Created by ISE for module: fsmCounter
  14. --
  15. -- Dependencies:
  16. --
  17. -- Revision:
  18. -- Revision 0.01 - File Created
  19. -- Additional Comments:
  20. --
  21. -- Notes:
  22. -- This testbench has been automatically generated using types std_logic and
  23. -- std_logic_vector for the ports of the unit under test.  Xilinx recommends
  24. -- that these types always be used for the top-level I/O of a design in order
  25. -- to guarantee that the testbench will bind correctly to the post-implementation
  26. -- simulation model.
  27. --------------------------------------------------------------------------------
  28. LIBRARY ieee;
  29. USE ieee.std_logic_1164.ALL;
  30.  
  31. -- Uncomment the following library declaration if using
  32. -- arithmetic functions with Signed or Unsigned values
  33. --USE ieee.numeric_std.ALL;
  34.  
  35. ENTITY counterTest IS
  36. END counterTest;
  37.  
  38. ARCHITECTURE behavior OF counterTest IS
  39.  
  40.     -- Component Declaration for the Unit Under Test (UUT)
  41.  
  42.     COMPONENT fsmCounter
  43.     PORT(
  44.          clk : IN  std_logic;
  45.          pb1 : IN  std_logic;
  46.          pb2 : IN  std_logic;
  47.          led : OUT  std_logic_vector(3 downto 0)
  48.         );
  49.     END COMPONENT;
  50.    
  51.  
  52.    --Inputs
  53.    signal clk : std_logic := '0';
  54.    signal pb1 : std_logic := '0';
  55.    signal pb2 : std_logic := '0';
  56.  
  57.     --Outputs
  58.    signal led : std_logic_vector(3 downto 0);
  59.  
  60.    -- Clock period definitions
  61.    constant clk_period : time := 10 ns;
  62.  
  63. BEGIN
  64.  
  65.     -- Instantiate the Unit Under Test (UUT)
  66.    uut: fsmCounter PORT MAP (
  67.           clk => clk,
  68.           pb1 => pb1,
  69.           pb2 => pb2,
  70.           led => led
  71.         );
  72.  
  73.    -- Clock process definitions
  74.    clk_process :process
  75.    begin
  76.         clk <= '0';
  77.         wait for clk_period/2;
  78.         clk <= '1';
  79.         wait for clk_period/2;
  80.    end process;
  81.  
  82.  
  83.    -- Stimulus process
  84.    stim_proc: process
  85.    begin       
  86.       -- hold reset state for 100 ns.
  87.       wait for 10 ns;  
  88.  
  89. --      wait for clk_period*10;
  90.  
  91.       -- insert stimulus here
  92.        
  93.         pb1 <= '1';
  94.         wait for 15 ns;
  95.         pb1 <= '0';
  96.         wait for 15 ns;
  97.         pb1 <= '1';
  98.         wait for 15 ns;
  99.         pb1 <= '0';
  100.         wait for 15 ns;
  101.         pb1 <= '1';
  102.         wait for 15 ns;
  103.         pb1 <= '0';
  104.         wait for 15 ns;
  105.         pb1 <= '1';
  106.         wait for 15 ns;
  107.         pb1 <= '0';
  108.         wait for 15 ns;
  109.         pb1 <= '1';
  110.         wait for 15 ns;
  111.         pb1 <= '0';
  112.         wait for 15 ns;
  113.         pb1 <= '1';
  114.         wait for 15 ns;
  115.         pb1 <= '0';
  116.         wait for 15 ns;
  117.         pb1 <= '1';
  118.         wait for 15 ns;
  119.         pb1 <= '0';
  120.         wait for 15 ns;
  121.         pb1 <= '1';
  122.         wait for 15 ns;
  123.         pb1 <= '0';
  124.         wait for 15 ns;
  125.         pb1 <= '1';
  126.         wait for 15 ns;
  127.         pb1 <= '0';
  128.         wait for 15 ns;
  129.         pb1 <= '1';
  130.         wait for 15 ns;
  131.         pb1 <= '0';
  132.         wait for 15 ns;
  133.         pb1 <= '1';
  134.         wait for 15 ns;
  135.         pb1 <= '0';
  136.         wait for 15 ns;
  137.         pb1 <= '1';
  138.         wait for 15 ns;
  139.         pb1 <= '0';
  140.         wait for 15 ns;
  141.         pb1 <= '1';
  142.         wait for 15 ns;
  143.         pb1 <= '0';
  144.         wait for 15 ns;
  145.         pb1 <= '1';
  146.         wait for 15 ns;
  147.         pb1 <= '0';
  148.         wait for 15 ns;
  149.         pb1 <= '1';
  150.         wait for 15 ns;
  151.         pb1 <= '0';
  152.         wait for 45 ns;
  153.         pb2 <= '1';
  154.         wait for 15 ns;
  155.         pb2 <= '0';
  156.         wait for 45 ns;
  157.         pb1 <= '1';
  158.         wait for 15 ns;
  159.         pb1 <= '0';
  160.         wait for 15 ns;
  161.         pb1 <= '1';
  162.         wait for 15 ns;
  163.         pb1 <= '0';
  164.         wait for 15 ns;
  165.        
  166.  
  167.  
  168.       wait;
  169.    end process;
  170.  
  171. END;
  172.  
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