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vedic_div32.syr.f949e3c77a

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May 6th, 2015
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  1. Release 14.4 - xst P.49d (lin64)
  2. Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
  3. -->
  4. Parameter TMPDIR set to xst/projnav.tmp
  5.  
  6.  
  7. Total REAL time to Xst completion: 1.00 secs
  8. Total CPU time to Xst completion: 0.08 secs
  9.  
  10. -->
  11. Parameter xsthdpdir set to xst
  12.  
  13.  
  14. Total REAL time to Xst completion: 1.00 secs
  15. Total CPU time to Xst completion: 0.08 secs
  16.  
  17. -->
  18. Reading design: vedic_div32.prj
  19.  
  20. TABLE OF CONTENTS
  21. 1) Synthesis Options Summary
  22. 2) HDL Compilation
  23. 3) Design Hierarchy Analysis
  24. 4) HDL Analysis
  25. 5) HDL Synthesis
  26. 5.1) HDL Synthesis Report
  27. 6) Advanced HDL Synthesis
  28. 6.1) Advanced HDL Synthesis Report
  29. 7) Low Level Synthesis
  30. 8) Partition Report
  31. 9) Final Report
  32. 9.1) Device utilization summary
  33. 9.2) Partition Resource Summary
  34. 9.3) TIMING REPORT
  35.  
  36.  
  37. =========================================================================
  38. * Synthesis Options Summary *
  39. =========================================================================
  40. ---- Source Parameters
  41. Input File Name : "vedic_div32.prj"
  42. Input Format : mixed
  43. Ignore Synthesis Constraint File : NO
  44.  
  45. ---- Target Parameters
  46. Output File Name : "vedic_div32"
  47. Output Format : NGC
  48. Target Device : xc5vlx50t-1-ff1136
  49.  
  50. ---- Source Options
  51. Top Module Name : vedic_div32
  52. Automatic FSM Extraction : YES
  53. FSM Encoding Algorithm : Auto
  54. Safe Implementation : No
  55. FSM Style : LUT
  56. RAM Extraction : Yes
  57. RAM Style : Auto
  58. ROM Extraction : Yes
  59. Mux Style : Auto
  60. Decoder Extraction : YES
  61. Priority Encoder Extraction : Yes
  62. Shift Register Extraction : YES
  63. Logical Shifter Extraction : YES
  64. XOR Collapsing : YES
  65. ROM Style : Auto
  66. Mux Extraction : Yes
  67. Resource Sharing : YES
  68. Asynchronous To Synchronous : NO
  69. Use DSP Block : Auto
  70. Automatic Register Balancing : No
  71.  
  72. ---- Target Options
  73. LUT Combining : Off
  74. Reduce Control Sets : Off
  75. Add IO Buffers : YES
  76. Global Maximum Fanout : 100000
  77. Add Generic Clock Buffer(BUFG) : 32
  78. Register Duplication : YES
  79. Slice Packing : YES
  80. Optimize Instantiated Primitives : NO
  81. Use Clock Enable : Auto
  82. Use Synchronous Set : Auto
  83. Use Synchronous Reset : Auto
  84. Pack IO Registers into IOBs : Auto
  85. Equivalent register Removal : YES
  86.  
  87. ---- General Options
  88. Optimization Goal : Speed
  89. Optimization Effort : 1
  90. Power Reduction : NO
  91. Keep Hierarchy : No
  92. Netlist Hierarchy : As_Optimized
  93. RTL Output : Yes
  94. Global Optimization : AllClockNets
  95. Read Cores : YES
  96. Write Timing Constraints : NO
  97. Cross Clock Analysis : NO
  98. Hierarchy Separator : /
  99. Bus Delimiter : <>
  100. Case Specifier : Maintain
  101. Slice Utilization Ratio : 100
  102. BRAM Utilization Ratio : 100
  103. DSP48 Utilization Ratio : 100
  104. Verilog 2001 : YES
  105. Auto BRAM Packing : NO
  106. Slice Utilization Ratio Delta : 5
  107.  
  108. =========================================================================
  109.  
  110.  
  111. =========================================================================
  112. * HDL Compilation *
  113. =========================================================================
  114. Compiling vhdl file "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" in Library work.
  115. Architecture rtl of Entity vedic_div32 is up to date.
  116.  
  117. =========================================================================
  118. * Design Hierarchy Analysis *
  119. =========================================================================
  120. Analyzing hierarchy for entity <vedic_div32> in library <work> (architecture <rtl>).
  121.  
  122.  
  123. =========================================================================
  124. * HDL Analysis *
  125. =========================================================================
  126. Analyzing Entity <vedic_div32> in library <work> (Architecture <rtl>).
  127. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 31-bit wide.
  128. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 1-bit wide.
  129. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 30-bit wide.
  130. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 2-bit wide.
  131. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 29-bit wide.
  132. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 3-bit wide.
  133. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 28-bit wide.
  134. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 4-bit wide.
  135. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 27-bit wide.
  136. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 5-bit wide.
  137. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 26-bit wide.
  138. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 6-bit wide.
  139. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 25-bit wide.
  140. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 7-bit wide.
  141. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 24-bit wide.
  142. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 8-bit wide.
  143. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 23-bit wide.
  144. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 9-bit wide.
  145. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 22-bit wide.
  146. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 10-bit wide.
  147. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 21-bit wide.
  148. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 11-bit wide.
  149. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 20-bit wide.
  150. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 12-bit wide.
  151. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 19-bit wide.
  152. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 13-bit wide.
  153. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 18-bit wide.
  154. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 14-bit wide.
  155. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 17-bit wide.
  156. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 15-bit wide.
  157. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 16-bit wide.
  158. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 16-bit wide.
  159. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 15-bit wide.
  160. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 17-bit wide.
  161. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 14-bit wide.
  162. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 18-bit wide.
  163. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 13-bit wide.
  164. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 19-bit wide.
  165. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 12-bit wide.
  166. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 20-bit wide.
  167. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 11-bit wide.
  168. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 21-bit wide.
  169. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 10-bit wide.
  170. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 22-bit wide.
  171. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 9-bit wide.
  172. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 23-bit wide.
  173. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 8-bit wide.
  174. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 24-bit wide.
  175. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 7-bit wide.
  176. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 25-bit wide.
  177. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 6-bit wide.
  178. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 26-bit wide.
  179. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 5-bit wide.
  180. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 27-bit wide.
  181. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 4-bit wide.
  182. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 28-bit wide.
  183. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 3-bit wide.
  184. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 29-bit wide.
  185. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 2-bit wide.
  186. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 30-bit wide.
  187. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 1-bit wide.
  188. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 31-bit wide.
  189. Entity <vedic_div32> analyzed. Unit <vedic_div32> generated.
  190.  
  191.  
  192. =========================================================================
  193. * HDL Synthesis *
  194. =========================================================================
  195.  
  196. Performing bidirectional port resolution...
  197.  
  198. Synthesizing Unit <vedic_div32>.
  199. Related source file is "/home/calros/enshu3-vedicdivider/vedic_div32.vhd".
  200. WARNING:Xst:653 - Signal <init_reg.quo> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
  201. Found finite state machine <FSM_0> for signal <state>.
  202. -----------------------------------------------------------------------
  203. | States | 4 |
  204. | Transitions | 9 |
  205. | Inputs | 3 |
  206. | Outputs | 4 |
  207. | Clock | mclk1 (rising_edge) |
  208. | Reset | state$and0000 (positive) |
  209. | Reset type | synchronous |
  210. | Reset State | fin_state |
  211. | Power Up State | init_state |
  212. | Encoding | automatic |
  213. | Implementation | LUT |
  214. -----------------------------------------------------------------------
  215. WARNING:Xst:737 - Found 5-bit latch for signal <shift_val>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  216. WARNING:Xst:737 - Found 36-bit latch for signal <init_reg.re_reg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  217. WARNING:Xst:737 - Found 31-bit latch for signal <b_n>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  218. WARNING:Xst:737 - Found 32-bit latch for signal <init_reg.quo_reg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  219. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 180: The result of a 33x3-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  220. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 180: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  221. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 180: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  222. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 180: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  223. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 180: The result of a 34x5-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  224. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 180: The result of a 34x5-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  225. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 180: The result of a 34x5-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  226. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 180: The result of a 34x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  227. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 196: The result of a 32x3-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  228. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 196: The result of a 32x3-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  229. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 196: The result of a 32x3-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  230. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 196: The result of a 32x2-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  231. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 104: The result of a 33x32-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  232. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 105: The result of a 33x32-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  233. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 180: The result of a 33x3-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  234. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 180: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  235. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 180: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  236. Found 34x4-bit multiplier for signal <$mult0000> created at line 180.
  237. Found 34x5-bit multiplier for signal <$mult0001> created at line 180.
  238. Found 34x5-bit multiplier for signal <$mult0002> created at line 180.
  239. Found 34x5-bit multiplier for signal <$mult0003> created at line 180.
  240. Found 31-bit shifter logical left for signal <b_n$shift0000> created at line 64.
  241. Found 5-bit register for signal <i>.
  242. Found 5-bit subtractor for signal <i$addsub0000> created at line 133.
  243. Found 32-bit register for signal <i_quo>.
  244. Found 32-bit register for signal <i_re>.
  245. Found 17-bit shifter logical left for signal <init_reg.re_reg$shift0047> created at line 70.
  246. Found 18-bit shifter logical left for signal <init_reg.re_reg$shift0048> created at line 70.
  247. Found 19-bit shifter logical left for signal <init_reg.re_reg$shift0049> created at line 70.
  248. Found 20-bit shifter logical left for signal <init_reg.re_reg$shift0050> created at line 70.
  249. Found 21-bit shifter logical left for signal <init_reg.re_reg$shift0051> created at line 70.
  250. Found 22-bit shifter logical left for signal <init_reg.re_reg$shift0052> created at line 70.
  251. Found 23-bit shifter logical left for signal <init_reg.re_reg$shift0053> created at line 70.
  252. Found 24-bit shifter logical left for signal <init_reg.re_reg$shift0054> created at line 70.
  253. Found 25-bit shifter logical left for signal <init_reg.re_reg$shift0055> created at line 70.
  254. Found 26-bit shifter logical left for signal <init_reg.re_reg$shift0056> created at line 70.
  255. Found 27-bit shifter logical left for signal <init_reg.re_reg$shift0057> created at line 70.
  256. Found 28-bit shifter logical left for signal <init_reg.re_reg$shift0058> created at line 70.
  257. Found 29-bit shifter logical left for signal <init_reg.re_reg$shift0059> created at line 70.
  258. Found 30-bit shifter logical left for signal <init_reg.re_reg$shift0060> created at line 70.
  259. Found 31-bit shifter logical left for signal <init_reg.re_reg$shift0061> created at line 70.
  260. Found 16-bit shifter logical left for signal <init_reg.re_reg$shift0062> created at line 70.
  261. Found 15-bit shifter logical left for signal <init_reg.re_reg$shift0063> created at line 70.
  262. Found 14-bit shifter logical left for signal <init_reg.re_reg$shift0064> created at line 70.
  263. Found 13-bit shifter logical left for signal <init_reg.re_reg$shift0065> created at line 70.
  264. Found 12-bit shifter logical left for signal <init_reg.re_reg$shift0066> created at line 70.
  265. Found 11-bit shifter logical left for signal <init_reg.re_reg$shift0067> created at line 70.
  266. Found 10-bit shifter logical left for signal <init_reg.re_reg$shift0068> created at line 70.
  267. Found 9-bit shifter logical left for signal <init_reg.re_reg$shift0069> created at line 70.
  268. Found 8-bit shifter logical left for signal <init_reg.re_reg$shift0070> created at line 70.
  269. Found 7-bit shifter logical left for signal <init_reg.re_reg$shift0071> created at line 70.
  270. Found 6-bit shifter logical left for signal <init_reg.re_reg$shift0072> created at line 70.
  271. Found 5-bit shifter logical left for signal <init_reg.re_reg$shift0073> created at line 70.
  272. Found 4-bit shifter logical left for signal <init_reg.re_reg$shift0074> created at line 70.
  273. Found 3-bit shifter logical left for signal <init_reg.re_reg$shift0075> created at line 70.
  274. Found 2-bit shifter logical left for signal <init_reg.re_reg$shift0076> created at line 70.
  275. Found 1-bit shifter logical left for signal <init_reg.re_reg$shift0077> created at line 70.
  276. Found 32-bit register for signal <k_reg.quo>.
  277. Found 36-bit register for signal <k_reg.re_reg>.
  278. Found 1-bit register for signal <k_reg.re_sign>.
  279. Found 32-bit register for signal <main_reg.quo>.
  280. Found 32-bit addsub for signal <main_reg.quo$mux0000>.
  281. Found 32-bit register for signal <main_reg.quo_reg>.
  282. Found 32-bit comparator greater for signal <main_reg.quo_reg$cmp_gt0000> created at line 110.
  283. Found 32-bit subtractor for signal <main_reg.quo_reg$mux0000>.
  284. Found 1-bit register for signal <main_reg.quo_sign>.
  285. Found 32-bit comparator greater for signal <main_reg.quo_sign$cmp_gt0000> created at line 110.
  286. Found 36-bit register for signal <main_reg.re_reg>.
  287. Found 36-bit comparator greater for signal <main_reg.re_reg$cmp_gt0000> created at line 120.
  288. Found 1-bit xor2 for signal <main_reg.re_reg$cmp_ne0000> created at line 119.
  289. Found 36-bit addsub for signal <main_reg.re_reg$mux0000>.
  290. Found 1-bit register for signal <main_reg.re_sign>.
  291. Found 32-bit comparator greatequal for signal <quo$cmp_ge0000> created at line 196.
  292. Found 32-bit comparator greatequal for signal <quo$cmp_ge0001> created at line 196.
  293. Found 32-bit comparator greatequal for signal <quo$cmp_ge0002> created at line 196.
  294. Found 32-bit comparator greatequal for signal <quo$cmp_ge0003> created at line 196.
  295. Found 32-bit comparator greatequal for signal <quo$cmp_ge0004> created at line 196.
  296. Found 32-bit comparator greatequal for signal <quo$cmp_ge0005> created at line 196.
  297. Found 32-bit comparator greatequal for signal <quo$cmp_ge0006> created at line 196.
  298. Found 32x2-bit multiplier for signal <quo$mult0004> created at line 196.
  299. Found 32x3-bit multiplier for signal <quo$mult0005> created at line 196.
  300. Found 32x3-bit multiplier for signal <quo$mult0006> created at line 196.
  301. Found 32x3-bit multiplier for signal <quo$mult0007> created at line 196.
  302. Found 32-bit addsub for signal <quo$share0000>.
  303. Found 33x32-bit multiplier for signal <quo_tmp$mult0001> created at line 104.
  304. Found 32-bit comparator greatequal for signal <re$cmp_ge0000> created at line 180.
  305. Found 32-bit comparator greatequal for signal <re$cmp_ge0001> created at line 180.
  306. Found 32-bit comparator greatequal for signal <re$cmp_ge0002> created at line 180.
  307. Found 32-bit comparator greatequal for signal <re$cmp_ge0003> created at line 180.
  308. Found 32-bit comparator greatequal for signal <re$cmp_ge0004> created at line 180.
  309. Found 32-bit comparator greatequal for signal <re$cmp_ge0005> created at line 180.
  310. Found 32-bit comparator greatequal for signal <re$cmp_ge0006> created at line 180.
  311. Found 32-bit comparator greatequal for signal <re$cmp_ge0007> created at line 180.
  312. Found 32-bit comparator greatequal for signal <re$cmp_ge0008> created at line 180.
  313. Found 32-bit comparator greatequal for signal <re$cmp_ge0009> created at line 180.
  314. Found 32-bit comparator greatequal for signal <re$cmp_ge0010> created at line 180.
  315. Found 32-bit comparator greatequal for signal <re$cmp_ge0011> created at line 180.
  316. Found 32-bit comparator greatequal for signal <re$cmp_ge0012> created at line 180.
  317. Found 32-bit comparator greatequal for signal <re$cmp_ge0013> created at line 180.
  318. Found 33x4-bit multiplier for signal <re$mult0004> created at line 180.
  319. Found 33x4-bit multiplier for signal <re$mult0005> created at line 180.
  320. Found 33x4-bit multiplier for signal <re$mult0006> created at line 180.
  321. Found 33x3-bit multiplier for signal <re$mult0007> created at line 180.
  322. Found 33x3-bit multiplier for signal <re$mult0008> created at line 180.
  323. Found 33x4-bit multiplier for signal <re$mult0009> created at line 180.
  324. Found 33x4-bit multiplier for signal <re$mult0010> created at line 180.
  325. Found 32-bit addsub for signal <re$share0000>.
  326. Found 32-bit adder for signal <re$sub0000> created at line 180.
  327. Found 32-bit adder for signal <re$sub0001> created at line 180.
  328. Found 32-bit adder for signal <re$sub0002> created at line 180.
  329. Found 32-bit adder for signal <re$sub0003> created at line 180.
  330. Found 32-bit adder for signal <re$sub0004> created at line 180.
  331. Found 32-bit adder for signal <re$sub0005> created at line 180.
  332. Found 33x32-bit multiplier for signal <re_tmp$mult0001> created at line 105.
  333. Found 30-bit 31-to-1 multiplexer for signal <re_tmp$mux0000<30:1>> created at line 105.
  334. Found 30-bit 31-to-1 multiplexer for signal <re_tmp$mux0000<0>> created at line 105.
  335. Found 32-bit shifter logical left for signal <re_tmp$shift0000> created at line 105.
  336. Found 32-bit shifter logical right for signal <tmp_quo_reg$shift0000> created at line 93.
  337. Found 36-bit adder for signal <v_re$addsub0000> created at line 170.
  338. Found 36-bit shifter arithmetic right for signal <v_re$shift0000> created at line 173.
  339. Found 32-bit shifter logical left for signal <v_reg.quo$shift0000> created at line 97.
  340. Found 1-bit 32-to-1 multiplexer for signal <v_reg.quo_reg_30$mux0000> created at line 102.
  341. Summary:
  342. inferred 1 Finite State Machine(s).
  343. inferred 240 D-type flip-flop(s).
  344. inferred 13 Adder/Subtractor(s).
  345. inferred 17 Multiplier(s).
  346. inferred 24 Comparator(s).
  347. inferred 32 Multiplexer(s).
  348. inferred 36 Combinational logic shifter(s).
  349. Unit <vedic_div32> synthesized.
  350.  
  351. INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
  352.  
  353. =========================================================================
  354. HDL Synthesis Report
  355.  
  356. Macro Statistics
  357. # Multipliers : 17
  358. 32x2-bit multiplier : 1
  359. 32x3-bit multiplier : 3
  360. 33x3-bit multiplier : 2
  361. 33x32-bit multiplier : 2
  362. 33x4-bit multiplier : 5
  363. 34x4-bit multiplier : 1
  364. 34x5-bit multiplier : 3
  365. # Adders/Subtractors : 13
  366. 32-bit adder : 6
  367. 32-bit addsub : 3
  368. 32-bit subtractor : 1
  369. 36-bit adder : 1
  370. 36-bit addsub : 1
  371. 5-bit subtractor : 1
  372. # Registers : 11
  373. 1-bit register : 3
  374. 32-bit register : 5
  375. 36-bit register : 2
  376. 5-bit register : 1
  377. # Latches : 4
  378. 31-bit latch : 1
  379. 32-bit latch : 1
  380. 36-bit latch : 1
  381. 5-bit latch : 1
  382. # Comparators : 24
  383. 32-bit comparator greatequal : 21
  384. 32-bit comparator greater : 2
  385. 36-bit comparator greater : 1
  386. # Multiplexers : 32
  387. 1-bit 31-to-1 multiplexer : 1
  388. 1-bit 32-to-1 multiplexer : 31
  389. # Logic shifters : 36
  390. 1-bit shifter logical left : 1
  391. 10-bit shifter logical left : 1
  392. 11-bit shifter logical left : 1
  393. 12-bit shifter logical left : 1
  394. 13-bit shifter logical left : 1
  395. 14-bit shifter logical left : 1
  396. 15-bit shifter logical left : 1
  397. 16-bit shifter logical left : 1
  398. 17-bit shifter logical left : 1
  399. 18-bit shifter logical left : 1
  400. 19-bit shifter logical left : 1
  401. 2-bit shifter logical left : 1
  402. 20-bit shifter logical left : 1
  403. 21-bit shifter logical left : 1
  404. 22-bit shifter logical left : 1
  405. 23-bit shifter logical left : 1
  406. 24-bit shifter logical left : 1
  407. 25-bit shifter logical left : 1
  408. 26-bit shifter logical left : 1
  409. 27-bit shifter logical left : 1
  410. 28-bit shifter logical left : 1
  411. 29-bit shifter logical left : 1
  412. 3-bit shifter logical left : 1
  413. 30-bit shifter logical left : 1
  414. 31-bit shifter logical left : 2
  415. 32-bit shifter logical left : 2
  416. 32-bit shifter logical right : 1
  417. 36-bit shifter arithmetic right : 1
  418. 4-bit shifter logical left : 1
  419. 5-bit shifter logical left : 1
  420. 6-bit shifter logical left : 1
  421. 7-bit shifter logical left : 1
  422. 8-bit shifter logical left : 1
  423. 9-bit shifter logical left : 1
  424. # Xors : 1
  425. 1-bit xor2 : 1
  426.  
  427. =========================================================================
  428.  
  429. =========================================================================
  430. * Advanced HDL Synthesis *
  431. =========================================================================
  432.  
  433. Analyzing FSM <FSM_0> for best encoding.
  434. Optimizing FSM <state/FSM> on signal <state[1:4]> with one-hot encoding.
  435. ------------------------
  436. State | Encoding
  437. ------------------------
  438. init_state | 0001
  439. main_state | 0100
  440. wait_state | 1000
  441. fin_state | 0010
  442. ------------------------
  443. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <31>. This FF/Latch will be trimmed during the optimization process.
  444. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <32>. This FF/Latch will be trimmed during the optimization process.
  445. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <33>. This FF/Latch will be trimmed during the optimization process.
  446. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <34>. This FF/Latch will be trimmed during the optimization process.
  447. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <35>. This FF/Latch will be trimmed during the optimization process.
  448.  
  449. Synthesizing (advanced) Unit <vedic_div32>.
  450. The following registers are absorbed into accumulator <main_reg.quo>: 1 register on signal <main_reg.quo>.
  451. Unit <vedic_div32> synthesized (advanced).
  452.  
  453. =========================================================================
  454. Advanced HDL Synthesis Report
  455.  
  456. Macro Statistics
  457. # FSMs : 1
  458. # Multipliers : 17
  459. 32x2-bit multiplier : 1
  460. 32x3-bit multiplier : 3
  461. 33x3-bit multiplier : 2
  462. 33x32-bit multiplier : 2
  463. 33x4-bit multiplier : 5
  464. 34x4-bit multiplier : 1
  465. 34x5-bit multiplier : 3
  466. # Adders/Subtractors : 12
  467. 32-bit adder : 6
  468. 32-bit addsub : 2
  469. 32-bit subtractor : 1
  470. 36-bit adder : 1
  471. 36-bit addsub : 1
  472. 5-bit subtractor : 1
  473. # Accumulators : 1
  474. 32-bit updown loadable accumulator : 1
  475. # Registers : 208
  476. Flip-Flops : 208
  477. # Latches : 4
  478. 31-bit latch : 1
  479. 32-bit latch : 1
  480. 36-bit latch : 1
  481. 5-bit latch : 1
  482. # Comparators : 24
  483. 32-bit comparator greatequal : 21
  484. 32-bit comparator greater : 2
  485. 36-bit comparator greater : 1
  486. # Multiplexers : 32
  487. 1-bit 31-to-1 multiplexer : 1
  488. 1-bit 32-to-1 multiplexer : 31
  489. # Logic shifters : 36
  490. 1-bit shifter logical left : 1
  491. 10-bit shifter logical left : 1
  492. 11-bit shifter logical left : 1
  493. 12-bit shifter logical left : 1
  494. 13-bit shifter logical left : 1
  495. 14-bit shifter logical left : 1
  496. 15-bit shifter logical left : 1
  497. 16-bit shifter logical left : 1
  498. 17-bit shifter logical left : 1
  499. 18-bit shifter logical left : 1
  500. 19-bit shifter logical left : 1
  501. 2-bit shifter logical left : 1
  502. 20-bit shifter logical left : 1
  503. 21-bit shifter logical left : 1
  504. 22-bit shifter logical left : 1
  505. 23-bit shifter logical left : 1
  506. 24-bit shifter logical left : 1
  507. 25-bit shifter logical left : 1
  508. 26-bit shifter logical left : 1
  509. 27-bit shifter logical left : 1
  510. 28-bit shifter logical left : 1
  511. 29-bit shifter logical left : 1
  512. 3-bit shifter logical left : 1
  513. 30-bit shifter logical left : 1
  514. 31-bit shifter logical left : 2
  515. 32-bit shifter logical left : 2
  516. 32-bit shifter logical right : 1
  517. 36-bit shifter arithmetic right : 1
  518. 4-bit shifter logical left : 1
  519. 5-bit shifter logical left : 1
  520. 6-bit shifter logical left : 1
  521. 7-bit shifter logical left : 1
  522. 8-bit shifter logical left : 1
  523. 9-bit shifter logical left : 1
  524. # Xors : 1
  525. 1-bit xor2 : 1
  526.  
  527. =========================================================================
  528.  
  529. =========================================================================
  530. * Low Level Synthesis *
  531. =========================================================================
  532. INFO:Xst:2261 - The FF/Latch <35> in Unit <LPM_LATCH_7> is equivalent to the following 4 FFs/Latches, which will be removed : <34> <33> <32> <31>
  533. WARNING:Xst:1293 - FF/Latch <35> has a constant value of 0 in block <LPM_LATCH_7>. This FF/Latch will be trimmed during the optimization process.
  534. WARNING:Xst:2677 - Node <Mmult_quo_tmp_mult00013> of sequential type is unconnected in block <vedic_div32>.
  535. WARNING:Xst:2677 - Node <Mmult_re_tmp_mult00013> of sequential type is unconnected in block <vedic_div32>.
  536.  
  537. Optimizing unit <vedic_div32> ...
  538.  
  539. Mapping all equations...
  540. Building and optimizing final netlist ...
  541. Found area constraint ratio of 100 (+ 5) on block vedic_div32, actual ratio is 16.
  542. FlipFlop i_2 has been replicated 1 time(s)
  543. FlipFlop i_3 has been replicated 1 time(s)
  544.  
  545. Final Macro Processing ...
  546.  
  547. =========================================================================
  548. Final Register Report
  549.  
  550. Macro Statistics
  551. # Registers : 245
  552. Flip-Flops : 245
  553.  
  554. =========================================================================
  555.  
  556. =========================================================================
  557. * Partition Report *
  558. =========================================================================
  559.  
  560. Partition Implementation Status
  561. -------------------------------
  562.  
  563. No Partitions were found in this design.
  564.  
  565. -------------------------------
  566.  
  567. =========================================================================
  568. * Final Report *
  569. =========================================================================
  570. Final Results
  571. RTL Top Level Output File Name : vedic_div32.ngr
  572. Top Level Output File Name : vedic_div32
  573. Output Format : NGC
  574. Optimization Goal : Speed
  575. Keep Hierarchy : No
  576.  
  577. Design Statistics
  578. # IOs : 130
  579.  
  580. Cell Usage :
  581. # BELS : 5802
  582. # GND : 1
  583. # INV : 190
  584. # LUT1 : 3
  585. # LUT2 : 680
  586. # LUT3 : 268
  587. # LUT4 : 826
  588. # LUT5 : 260
  589. # LUT6 : 1188
  590. # MUXCY : 1255
  591. # MUXF7 : 195
  592. # VCC : 1
  593. # XORCY : 935
  594. # FlipFlops/Latches : 344
  595. # FD : 156
  596. # FDE : 70
  597. # FDR : 2
  598. # FDS : 17
  599. # LDCP : 99
  600. # Clock Buffers : 2
  601. # BUFG : 1
  602. # BUFGP : 1
  603. # IO Buffers : 129
  604. # IBUF : 65
  605. # OBUF : 64
  606. # DSPs : 6
  607. # DSP48E : 6
  608. =========================================================================
  609.  
  610. Device utilization summary:
  611. ---------------------------
  612.  
  613. Selected Device : 5vlx50tff1136-1
  614.  
  615.  
  616. Slice Logic Utilization:
  617. Number of Slice Registers: 344 out of 28800 1%
  618. Number of Slice LUTs: 3415 out of 28800 11%
  619. Number used as Logic: 3415 out of 28800 11%
  620.  
  621. Slice Logic Distribution:
  622. Number of LUT Flip Flop pairs used: 3462
  623. Number with an unused Flip Flop: 3118 out of 3462 90%
  624. Number with an unused LUT: 47 out of 3462 1%
  625. Number of fully used LUT-FF pairs: 297 out of 3462 8%
  626. Number of unique control sets: 105
  627.  
  628. IO Utilization:
  629. Number of IOs: 130
  630. Number of bonded IOBs: 130 out of 480 27%
  631.  
  632. Specific Feature Utilization:
  633. Number of BUFG/BUFGCTRLs: 2 out of 32 6%
  634. Number of DSP48Es: 6 out of 48 12%
  635.  
  636. ---------------------------
  637. Partition Resource Summary:
  638. ---------------------------
  639.  
  640. No Partitions were found in this design.
  641.  
  642. ---------------------------
  643.  
  644.  
  645. =========================================================================
  646. TIMING REPORT
  647.  
  648. NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
  649. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
  650. GENERATED AFTER PLACE-and-ROUTE.
  651.  
  652. Clock Information:
  653. ------------------
  654. -----------------------------------+------------------------+-------+
  655. Clock Signal | Clock buffer(FF name) | Load |
  656. -----------------------------------+------------------------+-------+
  657. mclk1 | BUFGP | 245 |
  658. divisor<0> | IBUF+BUFG | 99 |
  659. -----------------------------------+------------------------+-------+
  660.  
  661. Asynchronous Control Signals Information:
  662. ----------------------------------------
  663. -------------------------------------------------------------+--------------------------+-------+
  664. Control Signal | Buffer(FF name) | Load |
  665. -------------------------------------------------------------+--------------------------+-------+
  666. Madd_re_sub0005_lut<0>(XST_GND:G) | NONE(init_reg.quo_reg_31)| 1 |
  667. Sh1538(Sh15381:O) | NONE(b_n_1) | 1 |
  668. Sh1539(Sh15391:O) | NONE(b_n_2) | 1 |
  669. b_n_0__and0000(b_n_0__and00001:O) | NONE(b_n_0) | 1 |
  670. b_n_0__and0001(b_n_0__and00011:O) | NONE(b_n_0) | 1 |
  671. b_n_10__and0000(b_n_10__and00001:O) | NONE(b_n_10) | 1 |
  672. b_n_10__and0001(b_n_10__and00011:O) | NONE(b_n_10) | 1 |
  673. b_n_11__and0000(b_n_11__and00001:O) | NONE(b_n_11) | 1 |
  674. b_n_11__and0001(b_n_11__and00011:O) | NONE(b_n_11) | 1 |
  675. b_n_12__and0000(b_n_12__and00001:O) | NONE(b_n_12) | 1 |
  676. b_n_12__and0001(b_n_12__and00011:O) | NONE(b_n_12) | 1 |
  677. b_n_13__and0000(b_n_13__and00001:O) | NONE(b_n_13) | 1 |
  678. b_n_13__and0001(b_n_13__and00011:O) | NONE(b_n_13) | 1 |
  679. b_n_14__and0000(b_n_14__and00001:O) | NONE(b_n_14) | 1 |
  680. b_n_14__and0001(b_n_14__and00011:O) | NONE(b_n_14) | 1 |
  681. b_n_15__and0000(b_n_15__and00001:O) | NONE(b_n_15) | 1 |
  682. b_n_15__and0001(b_n_15__and00011:O) | NONE(b_n_15) | 1 |
  683. b_n_16__and0000(b_n_16__and00001:O) | NONE(b_n_16) | 1 |
  684. b_n_16__and0001(b_n_16__and00011:O) | NONE(b_n_16) | 1 |
  685. b_n_17__and0000(b_n_17__and00001:O) | NONE(b_n_17) | 1 |
  686. b_n_17__and0001(b_n_17__and00011:O) | NONE(b_n_17) | 1 |
  687. b_n_18__and0000(b_n_18__and00001:O) | NONE(b_n_18) | 1 |
  688. b_n_18__and0001(b_n_18__and00011:O) | NONE(b_n_18) | 1 |
  689. b_n_19__and0000(b_n_19__and00001:O) | NONE(b_n_19) | 1 |
  690. b_n_19__and0001(b_n_19__and00011:O) | NONE(b_n_19) | 1 |
  691. b_n_1__and0000(b_n_1__and00001:O) | NONE(b_n_1) | 1 |
  692. b_n_20__and0000(b_n_20__and00001:O) | NONE(b_n_20) | 1 |
  693. b_n_20__and0001(b_n_20__and00011:O) | NONE(b_n_20) | 1 |
  694. b_n_21__and0000(b_n_21__and00001:O) | NONE(b_n_21) | 1 |
  695. b_n_21__and0001(b_n_21__and00011:O) | NONE(b_n_21) | 1 |
  696. b_n_22__and0000(b_n_22__and00001:O) | NONE(b_n_22) | 1 |
  697. b_n_22__and0001(b_n_22__and00011:O) | NONE(b_n_22) | 1 |
  698. b_n_23__and0000(b_n_23__and00001:O) | NONE(b_n_23) | 1 |
  699. b_n_23__and0001(b_n_23__and00011:O) | NONE(b_n_23) | 1 |
  700. b_n_24__and0000(b_n_24__and00001:O) | NONE(b_n_24) | 1 |
  701. b_n_24__and0001(b_n_24__and00011:O) | NONE(b_n_24) | 1 |
  702. b_n_25__and0000(b_n_25__and00001:O) | NONE(b_n_25) | 1 |
  703. b_n_25__and0001(b_n_25__and00011:O) | NONE(b_n_25) | 1 |
  704. b_n_26__and0000(b_n_26__and00001:O) | NONE(b_n_26) | 1 |
  705. b_n_26__and0001(b_n_26__and00011:O) | NONE(b_n_26) | 1 |
  706. b_n_27__and0000(b_n_27__and00001:O) | NONE(b_n_27) | 1 |
  707. b_n_27__and0001(b_n_27__and00011:O) | NONE(b_n_27) | 1 |
  708. b_n_28__and0000(b_n_28__and00001:O) | NONE(b_n_28) | 1 |
  709. b_n_28__and0001(b_n_28__and00011:O) | NONE(b_n_28) | 1 |
  710. b_n_29__and0000(b_n_29__and00001:O) | NONE(b_n_29) | 1 |
  711. b_n_29__and0001(b_n_29__and00011:O) | NONE(b_n_29) | 1 |
  712. b_n_2__and0000(b_n_2__and00001:O) | NONE(b_n_2) | 1 |
  713. b_n_30__and0000(b_n_30__and00001:O) | NONE(b_n_30) | 1 |
  714. b_n_30__and0001(b_n_30__and00011:O) | NONE(b_n_30) | 1 |
  715. b_n_3__and0000(b_n_3__and00001:O) | NONE(b_n_3) | 1 |
  716. b_n_3__and0001(b_n_3__and00011:O) | NONE(b_n_3) | 1 |
  717. b_n_4__and0000(b_n_4__and00001:O) | NONE(b_n_4) | 1 |
  718. b_n_4__and0001(b_n_4__and00011:O) | NONE(b_n_4) | 1 |
  719. b_n_5__and0000(b_n_5__and00001:O) | NONE(b_n_5) | 1 |
  720. b_n_5__and0001(b_n_5__and00011:O) | NONE(b_n_5) | 1 |
  721. b_n_6__and0000(b_n_6__and00001:O) | NONE(b_n_6) | 1 |
  722. b_n_6__and0001(b_n_6__and00011:O) | NONE(b_n_6) | 1 |
  723. b_n_7__and0000(b_n_7__and00001:O) | NONE(b_n_7) | 1 |
  724. b_n_7__and0001(b_n_7__and00011:O) | NONE(b_n_7) | 1 |
  725. b_n_8__and0000(b_n_8__and00001:O) | NONE(b_n_8) | 1 |
  726. b_n_8__and0001(b_n_8__and00011:O) | NONE(b_n_8) | 1 |
  727. b_n_9__and0000(b_n_9__and00001:O) | NONE(b_n_9) | 1 |
  728. b_n_9__and0001(b_n_9__and00011:O) | NONE(b_n_9) | 1 |
  729. init_reg.quo_reg_0__and0000(init_reg.quo_reg_0__and00001:O) | NONE(init_reg.quo_reg_0) | 1 |
  730. init_reg.quo_reg_0__and0001(init_reg.quo_reg_0__and00011:O) | NONE(init_reg.quo_reg_0) | 1 |
  731. init_reg.quo_reg_10__and0000(init_reg.quo_reg_10__and00001:O)| NONE(init_reg.quo_reg_10)| 1 |
  732. init_reg.quo_reg_10__and0001(init_reg.quo_reg_10__and00011:O)| NONE(init_reg.quo_reg_10)| 1 |
  733. init_reg.quo_reg_11__and0000(init_reg.quo_reg_11__and00001:O)| NONE(init_reg.quo_reg_11)| 1 |
  734. init_reg.quo_reg_11__and0001(init_reg.quo_reg_11__and00011:O)| NONE(init_reg.quo_reg_11)| 1 |
  735. init_reg.quo_reg_12__and0000(init_reg.quo_reg_12__and00001:O)| NONE(init_reg.quo_reg_12)| 1 |
  736. init_reg.quo_reg_12__and0001(init_reg.quo_reg_12__and00011:O)| NONE(init_reg.quo_reg_12)| 1 |
  737. init_reg.quo_reg_13__and0000(init_reg.quo_reg_13__and00001:O)| NONE(init_reg.quo_reg_13)| 1 |
  738. init_reg.quo_reg_13__and0001(init_reg.quo_reg_13__and00011:O)| NONE(init_reg.quo_reg_13)| 1 |
  739. init_reg.quo_reg_14__and0000(init_reg.quo_reg_14__and00001:O)| NONE(init_reg.quo_reg_14)| 1 |
  740. init_reg.quo_reg_14__and0001(init_reg.quo_reg_14__and00011:O)| NONE(init_reg.quo_reg_14)| 1 |
  741. init_reg.quo_reg_15__and0000(init_reg.quo_reg_15__and00001:O)| NONE(init_reg.quo_reg_15)| 1 |
  742. init_reg.quo_reg_15__and0001(init_reg.quo_reg_15__and00011:O)| NONE(init_reg.quo_reg_15)| 1 |
  743. init_reg.quo_reg_16__and0000(init_reg.quo_reg_16__and00001:O)| NONE(init_reg.quo_reg_16)| 1 |
  744. init_reg.quo_reg_16__and0001(init_reg.quo_reg_16__and00011:O)| NONE(init_reg.quo_reg_16)| 1 |
  745. init_reg.quo_reg_17__and0000(init_reg.quo_reg_17__and00001:O)| NONE(init_reg.quo_reg_17)| 1 |
  746. init_reg.quo_reg_17__and0001(init_reg.quo_reg_17__and00011:O)| NONE(init_reg.quo_reg_17)| 1 |
  747. init_reg.quo_reg_18__and0000(init_reg.quo_reg_18__and00001:O)| NONE(init_reg.quo_reg_18)| 1 |
  748. init_reg.quo_reg_18__and0001(init_reg.quo_reg_18__and00011:O)| NONE(init_reg.quo_reg_18)| 1 |
  749. init_reg.quo_reg_19__and0000(init_reg.quo_reg_19__and00001:O)| NONE(init_reg.quo_reg_19)| 1 |
  750. init_reg.quo_reg_19__and0001(init_reg.quo_reg_19__and00011:O)| NONE(init_reg.quo_reg_19)| 1 |
  751. init_reg.quo_reg_1__and0000(init_reg.quo_reg_1__and00001:O) | NONE(init_reg.quo_reg_1) | 1 |
  752. init_reg.quo_reg_1__and0001(init_reg.quo_reg_1__and00011:O) | NONE(init_reg.quo_reg_1) | 1 |
  753. init_reg.quo_reg_20__and0000(init_reg.quo_reg_20__and00001:O)| NONE(init_reg.quo_reg_20)| 1 |
  754. init_reg.quo_reg_20__and0001(init_reg.quo_reg_20__and00011:O)| NONE(init_reg.quo_reg_20)| 1 |
  755. init_reg.quo_reg_21__and0000(init_reg.quo_reg_21__and00001:O)| NONE(init_reg.quo_reg_21)| 1 |
  756. init_reg.quo_reg_21__and0001(init_reg.quo_reg_21__and00011:O)| NONE(init_reg.quo_reg_21)| 1 |
  757. init_reg.quo_reg_22__and0000(init_reg.quo_reg_22__and00001:O)| NONE(init_reg.quo_reg_22)| 1 |
  758. init_reg.quo_reg_22__and0001(init_reg.quo_reg_22__and00011:O)| NONE(init_reg.quo_reg_22)| 1 |
  759. init_reg.quo_reg_23__and0000(init_reg.quo_reg_23__and00001:O)| NONE(init_reg.quo_reg_23)| 1 |
  760. init_reg.quo_reg_23__and0001(init_reg.quo_reg_23__and00011:O)| NONE(init_reg.quo_reg_23)| 1 |
  761. init_reg.quo_reg_24__and0000(init_reg.quo_reg_24__and00001:O)| NONE(init_reg.quo_reg_24)| 1 |
  762. init_reg.quo_reg_24__and0001(init_reg.quo_reg_24__and00011:O)| NONE(init_reg.quo_reg_24)| 1 |
  763. init_reg.quo_reg_25__and0000(init_reg.quo_reg_25__and00001:O)| NONE(init_reg.quo_reg_25)| 1 |
  764. init_reg.quo_reg_25__and0001(init_reg.quo_reg_25__and00011:O)| NONE(init_reg.quo_reg_25)| 1 |
  765. init_reg.quo_reg_26__and0000(init_reg.quo_reg_26__and00001:O)| NONE(init_reg.quo_reg_26)| 1 |
  766. init_reg.quo_reg_26__and0001(init_reg.quo_reg_26__and00011:O)| NONE(init_reg.quo_reg_26)| 1 |
  767. init_reg.quo_reg_27__and0000(init_reg.quo_reg_27__and00001:O)| NONE(init_reg.quo_reg_27)| 1 |
  768. init_reg.quo_reg_27__and0001(init_reg.quo_reg_27__and00011:O)| NONE(init_reg.quo_reg_27)| 1 |
  769. init_reg.quo_reg_28__and0000(init_reg.quo_reg_28__and00001:O)| NONE(init_reg.quo_reg_28)| 1 |
  770. init_reg.quo_reg_28__and0001(init_reg.quo_reg_28__and00011:O)| NONE(init_reg.quo_reg_28)| 1 |
  771. init_reg.quo_reg_29__and0000(init_reg.quo_reg_29__and00001:O)| NONE(init_reg.quo_reg_29)| 1 |
  772. init_reg.quo_reg_29__and0001(init_reg.quo_reg_29__and00011:O)| NONE(init_reg.quo_reg_29)| 1 |
  773. init_reg.quo_reg_2__and0000(init_reg.quo_reg_2__and00001:O) | NONE(init_reg.quo_reg_2) | 1 |
  774. init_reg.quo_reg_2__and0001(init_reg.quo_reg_2__and00011:O) | NONE(init_reg.quo_reg_2) | 1 |
  775. init_reg.quo_reg_30__and0000(init_reg.quo_reg_30__and00001:O)| NONE(init_reg.quo_reg_30)| 1 |
  776. init_reg.quo_reg_30__and0001(init_reg.quo_reg_30__and00011:O)| NONE(init_reg.quo_reg_30)| 1 |
  777. init_reg.quo_reg_3__and0000(init_reg.quo_reg_3__and00001:O) | NONE(init_reg.quo_reg_3) | 1 |
  778. init_reg.quo_reg_3__and0001(init_reg.quo_reg_3__and00011:O) | NONE(init_reg.quo_reg_3) | 1 |
  779. init_reg.quo_reg_4__and0000(init_reg.quo_reg_4__and00001:O) | NONE(init_reg.quo_reg_4) | 1 |
  780. init_reg.quo_reg_4__and0001(init_reg.quo_reg_4__and00011:O) | NONE(init_reg.quo_reg_4) | 1 |
  781. init_reg.quo_reg_5__and0000(init_reg.quo_reg_5__and00001:O) | NONE(init_reg.quo_reg_5) | 1 |
  782. init_reg.quo_reg_5__and0001(init_reg.quo_reg_5__and00011:O) | NONE(init_reg.quo_reg_5) | 1 |
  783. init_reg.quo_reg_6__and0000(init_reg.quo_reg_6__and00001:O) | NONE(init_reg.quo_reg_6) | 1 |
  784. init_reg.quo_reg_6__and0001(init_reg.quo_reg_6__and00011:O) | NONE(init_reg.quo_reg_6) | 1 |
  785. init_reg.quo_reg_7__and0000(init_reg.quo_reg_7__and00001:O) | NONE(init_reg.quo_reg_7) | 1 |
  786. init_reg.quo_reg_7__and0001(init_reg.quo_reg_7__and00011:O) | NONE(init_reg.quo_reg_7) | 1 |
  787. init_reg.quo_reg_8__and0000(init_reg.quo_reg_8__and00001:O) | NONE(init_reg.quo_reg_8) | 1 |
  788. init_reg.quo_reg_8__and0001(init_reg.quo_reg_8__and00011:O) | NONE(init_reg.quo_reg_8) | 1 |
  789. init_reg.quo_reg_9__and0000(init_reg.quo_reg_9__and00001:O) | NONE(init_reg.quo_reg_9) | 1 |
  790. init_reg.quo_reg_9__and0001(init_reg.quo_reg_9__and00011:O) | NONE(init_reg.quo_reg_9) | 1 |
  791. init_reg.re_reg_0__and0000(init_reg.re_reg_0__and00001:O) | NONE(init_reg.re_reg_0) | 1 |
  792. init_reg.re_reg_0__and0001(init_reg.re_reg_0__and00011:O) | NONE(init_reg.re_reg_0) | 1 |
  793. init_reg.re_reg_10__and0000(init_reg.re_reg_10__and00001:O) | NONE(init_reg.re_reg_10) | 1 |
  794. init_reg.re_reg_10__and0001(init_reg.re_reg_10__and00011:O) | NONE(init_reg.re_reg_10) | 1 |
  795. init_reg.re_reg_11__and0000(init_reg.re_reg_11__and00001:O) | NONE(init_reg.re_reg_11) | 1 |
  796. init_reg.re_reg_11__and0001(init_reg.re_reg_11__and00011:O) | NONE(init_reg.re_reg_11) | 1 |
  797. init_reg.re_reg_12__and0000(init_reg.re_reg_12__and00001:O) | NONE(init_reg.re_reg_12) | 1 |
  798. init_reg.re_reg_12__and0001(init_reg.re_reg_12__and00011:O) | NONE(init_reg.re_reg_12) | 1 |
  799. init_reg.re_reg_13__and0000(init_reg.re_reg_13__and00001:O) | NONE(init_reg.re_reg_13) | 1 |
  800. init_reg.re_reg_13__and0001(init_reg_re_reg_mux0031<13>2:O) | NONE(init_reg.re_reg_13) | 1 |
  801. init_reg.re_reg_14__and0000(init_reg.re_reg_14__and00001:O) | NONE(init_reg.re_reg_14) | 1 |
  802. init_reg.re_reg_14__and0001(init_reg.re_reg_14__and00011:O) | NONE(init_reg.re_reg_14) | 1 |
  803. init_reg.re_reg_15__and0000(init_reg.re_reg_15__and00001:O) | NONE(init_reg.re_reg_15) | 1 |
  804. init_reg.re_reg_15__and0001(init_reg.re_reg_15__and00011:O) | NONE(init_reg.re_reg_15) | 1 |
  805. init_reg.re_reg_16__and0000(init_reg.re_reg_16__and00001:O) | NONE(init_reg.re_reg_16) | 1 |
  806. init_reg.re_reg_16__and0001(init_reg.re_reg_16__and00011:O) | NONE(init_reg.re_reg_16) | 1 |
  807. init_reg.re_reg_17__and0000(init_reg.re_reg_17__and00001:O) | NONE(init_reg.re_reg_17) | 1 |
  808. init_reg.re_reg_17__and0001(init_reg.re_reg_17__and00011:O) | NONE(init_reg.re_reg_17) | 1 |
  809. init_reg.re_reg_18__and0000(init_reg.re_reg_18__and00001:O) | NONE(init_reg.re_reg_18) | 1 |
  810. init_reg.re_reg_18__and0001(init_reg.re_reg_18__and00011:O) | NONE(init_reg.re_reg_18) | 1 |
  811. init_reg.re_reg_19__and0000(init_reg.re_reg_19__and00001:O) | NONE(init_reg.re_reg_19) | 1 |
  812. init_reg.re_reg_19__and0001(init_reg.re_reg_19__and00011:O) | NONE(init_reg.re_reg_19) | 1 |
  813. init_reg.re_reg_1__and0000(init_reg.re_reg_1__and00001:O) | NONE(init_reg.re_reg_1) | 1 |
  814. init_reg.re_reg_1__and0001(init_reg.re_reg_1__and00011:O) | NONE(init_reg.re_reg_1) | 1 |
  815. init_reg.re_reg_20__and0000(init_reg.re_reg_20__and00001:O) | NONE(init_reg.re_reg_20) | 1 |
  816. init_reg.re_reg_20__and0001(init_reg.re_reg_20__and00011:O) | NONE(init_reg.re_reg_20) | 1 |
  817. init_reg.re_reg_21__and0000(init_reg.re_reg_21__and00001:O) | NONE(init_reg.re_reg_21) | 1 |
  818. init_reg.re_reg_21__and0001(init_reg.re_reg_21__and00011:O) | NONE(init_reg.re_reg_21) | 1 |
  819. init_reg.re_reg_22__and0000(init_reg.re_reg_22__and00001:O) | NONE(init_reg.re_reg_22) | 1 |
  820. init_reg.re_reg_22__and0001(init_reg.re_reg_22__and00011:O) | NONE(init_reg.re_reg_22) | 1 |
  821. init_reg.re_reg_23__and0000(init_reg.re_reg_23__and00001:O) | NONE(init_reg.re_reg_23) | 1 |
  822. init_reg.re_reg_23__and0001(init_reg.re_reg_23__and00011:O) | NONE(init_reg.re_reg_23) | 1 |
  823. init_reg.re_reg_24__and0000(init_reg.re_reg_24__and00001:O) | NONE(init_reg.re_reg_24) | 1 |
  824. init_reg.re_reg_24__and0001(init_reg.re_reg_24__and00011:O) | NONE(init_reg.re_reg_24) | 1 |
  825. init_reg.re_reg_25__and0000(init_reg.re_reg_25__and00001:O) | NONE(init_reg.re_reg_25) | 1 |
  826. init_reg.re_reg_25__and0001(init_reg.re_reg_25__and00011:O) | NONE(init_reg.re_reg_25) | 1 |
  827. init_reg.re_reg_26__and0000(init_reg.re_reg_26__and00001:O) | NONE(init_reg.re_reg_26) | 1 |
  828. init_reg.re_reg_26__and0001(init_reg.re_reg_26__and00011:O) | NONE(init_reg.re_reg_26) | 1 |
  829. init_reg.re_reg_27__and0000(init_reg.re_reg_27__and00001:O) | NONE(init_reg.re_reg_27) | 1 |
  830. init_reg.re_reg_27__and0001(init_reg.re_reg_27__and00011:O) | NONE(init_reg.re_reg_27) | 1 |
  831. init_reg.re_reg_28__and0000(init_reg.re_reg_28__and00001:O) | NONE(init_reg.re_reg_28) | 1 |
  832. init_reg.re_reg_28__and0001(init_reg.re_reg_28__and00011:O) | NONE(init_reg.re_reg_28) | 1 |
  833. init_reg.re_reg_29__and0000(init_reg.re_reg_29__and00001:O) | NONE(init_reg.re_reg_29) | 1 |
  834. init_reg.re_reg_29__and0001(init_reg.re_reg_29__and00011:O) | NONE(init_reg.re_reg_29) | 1 |
  835. init_reg.re_reg_2__and0000(init_reg.re_reg_2__and00001:O) | NONE(init_reg.re_reg_2) | 1 |
  836. init_reg.re_reg_2__and0001(init_reg.re_reg_2__and00011:O) | NONE(init_reg.re_reg_2) | 1 |
  837. init_reg.re_reg_30__and0000(init_reg.re_reg_30__and00001:O) | NONE(init_reg.re_reg_30) | 1 |
  838. init_reg.re_reg_30__and0001(init_reg.re_reg_30__and00011:O) | NONE(init_reg.re_reg_30) | 1 |
  839. init_reg.re_reg_3__and0000(init_reg.re_reg_3__and00001:O) | NONE(init_reg.re_reg_3) | 1 |
  840. init_reg.re_reg_3__and0001(init_reg.re_reg_3__and00011:O) | NONE(init_reg.re_reg_3) | 1 |
  841. init_reg.re_reg_4__and0000(init_reg.re_reg_4__and00001:O) | NONE(init_reg.re_reg_4) | 1 |
  842. init_reg.re_reg_4__and0001(init_reg.re_reg_4__and00011:O) | NONE(init_reg.re_reg_4) | 1 |
  843. init_reg.re_reg_5__and0000(init_reg.re_reg_5__and00001:O) | NONE(init_reg.re_reg_5) | 1 |
  844. init_reg.re_reg_5__and0001(init_reg.re_reg_5__and00011:O) | NONE(init_reg.re_reg_5) | 1 |
  845. init_reg.re_reg_6__and0000(init_reg.re_reg_6__and00001:O) | NONE(init_reg.re_reg_6) | 1 |
  846. init_reg.re_reg_6__and0001(init_reg.re_reg_6__and00011:O) | NONE(init_reg.re_reg_6) | 1 |
  847. init_reg.re_reg_7__and0000(init_reg.re_reg_7__and00001:O) | NONE(init_reg.re_reg_7) | 1 |
  848. init_reg.re_reg_7__and0001(init_reg.re_reg_7__and00011:O) | NONE(init_reg.re_reg_7) | 1 |
  849. init_reg.re_reg_8__and0000(init_reg.re_reg_8__and00001:O) | NONE(init_reg.re_reg_8) | 1 |
  850. init_reg.re_reg_8__and0001(init_reg.re_reg_8__and00011:O) | NONE(init_reg.re_reg_8) | 1 |
  851. init_reg.re_reg_9__and0000(init_reg.re_reg_9__and00001:O) | NONE(init_reg.re_reg_9) | 1 |
  852. init_reg.re_reg_9__and0001(init_reg.re_reg_9__and00011:O) | NONE(init_reg.re_reg_9) | 1 |
  853. init_reg_re_reg_or0001(init_reg_re_reg_or00011:O) | NONE(init_reg.quo_reg_31)| 1 |
  854. shift_val_0__or0000(shift_val_0__or00001:O) | NONE(shift_val_0) | 1 |
  855. shift_val_0__or0001(shift_val_0__or00011:O) | NONE(shift_val_0) | 1 |
  856. shift_val_1__and0000(shift_val_1__and00001:O) | NONE(shift_val_1) | 1 |
  857. shift_val_1__or0000(shift_val_1__or00001:O) | NONE(shift_val_1) | 1 |
  858. shift_val_2__and0000(shift_val_2__and00001:O) | NONE(shift_val_2) | 1 |
  859. shift_val_2__or0000(shift_val_2__or00001:O) | NONE(shift_val_2) | 1 |
  860. shift_val_3__and0000(shift_val_3__and00001:O) | NONE(shift_val_3) | 1 |
  861. shift_val_3__or0000(shift_val_3__or00001:O) | NONE(shift_val_3) | 1 |
  862. shift_val_4__and0000(shift_val_4__and00001:O) | NONE(shift_val_4) | 1 |
  863. shift_val_4__or0000(shift_val_4__or00001:O) | NONE(shift_val_4) | 1 |
  864. -------------------------------------------------------------+--------------------------+-------+
  865.  
  866. Timing Summary:
  867. ---------------
  868. Speed Grade: -1
  869.  
  870. Minimum period: 17.600ns (Maximum Frequency: 56.817MHz)
  871. Minimum input arrival time before clock: 7.365ns
  872. Maximum output required time after clock: 12.160ns
  873. Maximum combinational path delay: 15.580ns
  874.  
  875. Timing Detail:
  876. --------------
  877. All values displayed in nanoseconds (ns)
  878.  
  879. =========================================================================
  880. Timing constraint: Default period analysis for Clock 'mclk1'
  881. Clock period: 17.600ns (frequency: 56.817MHz)
  882. Total number of paths / destination ports: 452698665648 / 334
  883. -------------------------------------------------------------------------
  884. Delay: 17.600ns (Levels of Logic = 53)
  885. Source: state_FSM_FFd4 (FF)
  886. Destination: main_reg.re_reg_35 (FF)
  887. Source Clock: mclk1 rising
  888. Destination Clock: mclk1 rising
  889.  
  890. Data Path: state_FSM_FFd4 to main_reg.re_reg_35
  891. Gate Net
  892. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  893. ---------------------------------------- ------------
  894. FDR:C->Q 281 0.471 1.242 state_FSM_FFd4 (state_FSM_FFd4)
  895. LUT6:I0->O 1 0.094 0.000 Sh14651_F (N1252)
  896. MUXF7:I0->O 8 0.251 1.011 Sh14651 (Sh1465)
  897. LUT6:I1->O 1 0.094 0.000 Sh1505161_G (N1209)
  898. MUXF7:I1->O 12 0.254 0.396 Sh1505161 (Sh1505)
  899. DSP48E:B0->PCOUT37 1 3.832 0.000 Mmult_re_tmp_mult0001 (Mmult_re_tmp_mult0001_PCOUT_to_Mmult_re_tmp_mult00011_PCIN_37)
  900. DSP48E:PCIN37->PCOUT8 1 2.013 0.000 Mmult_re_tmp_mult00011 (Mmult_re_tmp_mult00011_PCOUT_to_Mmult_re_tmp_mult00012_PCIN_8)
  901. DSP48E:PCIN8->P1 4 1.816 0.805 Mmult_re_tmp_mult00012 (re_tmp_mult0001<18>)
  902. LUT6:I2->O 3 0.094 0.984 Sh17471 (Sh1747)
  903. LUT6:I1->O 1 0.094 0.000 Sh1815_F (N1200)
  904. MUXF7:I0->O 4 0.251 0.805 Sh1815 (Sh1815)
  905. LUT4:I0->O 0 0.094 0.000 Mcompar_main_reg.re_reg_cmp_gt0000_lutdi12 (Mcompar_main_reg.re_reg_cmp_gt0000_lutdi12)
  906. MUXCY:DI->O 1 0.362 0.000 Mcompar_main_reg.re_reg_cmp_gt0000_cy<12> (Mcompar_main_reg.re_reg_cmp_gt0000_cy<12>)
  907. MUXCY:CI->O 1 0.026 0.000 Mcompar_main_reg.re_reg_cmp_gt0000_cy<13> (Mcompar_main_reg.re_reg_cmp_gt0000_cy<13>)
  908. MUXCY:CI->O 1 0.026 0.000 Mcompar_main_reg.re_reg_cmp_gt0000_cy<14> (Mcompar_main_reg.re_reg_cmp_gt0000_cy<14>)
  909. MUXCY:CI->O 1 0.026 0.000 Mcompar_main_reg.re_reg_cmp_gt0000_cy<15> (Mcompar_main_reg.re_reg_cmp_gt0000_cy<15>)
  910. MUXCY:CI->O 36 0.254 0.608 Mcompar_main_reg.re_reg_cmp_gt0000_cy<16> (Mcompar_main_reg.re_reg_cmp_gt0000_cy<16>)
  911. LUT6:I5->O 0 0.094 0.000 main_reg_re_reg_mux0001<0>1 (main_reg_re_reg_mux0001<0>)
  912. MUXCY:DI->O 1 0.362 0.000 Maddsub_main_reg.re_reg_mux0000_cy<0> (Maddsub_main_reg.re_reg_mux0000_cy<0>)
  913. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<1> (Maddsub_main_reg.re_reg_mux0000_cy<1>)
  914. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<2> (Maddsub_main_reg.re_reg_mux0000_cy<2>)
  915. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<3> (Maddsub_main_reg.re_reg_mux0000_cy<3>)
  916. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<4> (Maddsub_main_reg.re_reg_mux0000_cy<4>)
  917. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<5> (Maddsub_main_reg.re_reg_mux0000_cy<5>)
  918. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<6> (Maddsub_main_reg.re_reg_mux0000_cy<6>)
  919. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<7> (Maddsub_main_reg.re_reg_mux0000_cy<7>)
  920. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<8> (Maddsub_main_reg.re_reg_mux0000_cy<8>)
  921. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<9> (Maddsub_main_reg.re_reg_mux0000_cy<9>)
  922. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<10> (Maddsub_main_reg.re_reg_mux0000_cy<10>)
  923. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<11> (Maddsub_main_reg.re_reg_mux0000_cy<11>)
  924. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<12> (Maddsub_main_reg.re_reg_mux0000_cy<12>)
  925. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<13> (Maddsub_main_reg.re_reg_mux0000_cy<13>)
  926. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<14> (Maddsub_main_reg.re_reg_mux0000_cy<14>)
  927. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<15> (Maddsub_main_reg.re_reg_mux0000_cy<15>)
  928. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<16> (Maddsub_main_reg.re_reg_mux0000_cy<16>)
  929. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<17> (Maddsub_main_reg.re_reg_mux0000_cy<17>)
  930. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<18> (Maddsub_main_reg.re_reg_mux0000_cy<18>)
  931. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<19> (Maddsub_main_reg.re_reg_mux0000_cy<19>)
  932. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<20> (Maddsub_main_reg.re_reg_mux0000_cy<20>)
  933. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<21> (Maddsub_main_reg.re_reg_mux0000_cy<21>)
  934. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<22> (Maddsub_main_reg.re_reg_mux0000_cy<22>)
  935. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<23> (Maddsub_main_reg.re_reg_mux0000_cy<23>)
  936. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<24> (Maddsub_main_reg.re_reg_mux0000_cy<24>)
  937. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<25> (Maddsub_main_reg.re_reg_mux0000_cy<25>)
  938. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<26> (Maddsub_main_reg.re_reg_mux0000_cy<26>)
  939. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<27> (Maddsub_main_reg.re_reg_mux0000_cy<27>)
  940. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<28> (Maddsub_main_reg.re_reg_mux0000_cy<28>)
  941. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<29> (Maddsub_main_reg.re_reg_mux0000_cy<29>)
  942. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<30> (Maddsub_main_reg.re_reg_mux0000_cy<30>)
  943. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<31> (Maddsub_main_reg.re_reg_mux0000_cy<31>)
  944. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<32> (Maddsub_main_reg.re_reg_mux0000_cy<32>)
  945. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<33> (Maddsub_main_reg.re_reg_mux0000_cy<33>)
  946. MUXCY:CI->O 0 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<34> (Maddsub_main_reg.re_reg_mux0000_cy<34>)
  947. XORCY:CI->O 1 0.357 0.000 Maddsub_main_reg.re_reg_mux0000_xor<35> (main_reg_re_reg_mux0000<35>)
  948. FD:D -0.018 main_reg.re_reg_35
  949. ----------------------------------------
  950. Total 17.600ns (11.749ns logic, 5.851ns route)
  951. (66.8% logic, 33.2% route)
  952.  
  953. =========================================================================
  954. Timing constraint: Default period analysis for Clock 'divisor<0>'
  955. Clock period: 4.457ns (frequency: 224.362MHz)
  956. Total number of paths / destination ports: 935 / 62
  957. -------------------------------------------------------------------------
  958. Delay: 4.457ns (Levels of Logic = 4)
  959. Source: shift_val_1 (LATCH)
  960. Destination: init_reg.re_reg_14 (LATCH)
  961. Source Clock: divisor<0> falling
  962. Destination Clock: divisor<0> falling
  963.  
  964. Data Path: shift_val_1 to init_reg.re_reg_14
  965. Gate Net
  966. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  967. ---------------------------------------- ------------
  968. LDCP:G->Q 101 0.736 1.209 shift_val_1 (shift_val_1)
  969. LUT6:I0->O 5 0.094 0.995 Sh10351 (Sh1035)
  970. LUT6:I1->O 3 0.094 0.984 Sh10071 (Sh1007)
  971. LUT6:I1->O 1 0.094 0.000 init_reg_re_reg_mux0031<14>1 (init_reg_re_reg_mux0031<14>1)
  972. MUXF7:I0->O 3 0.251 0.000 init_reg_re_reg_mux0031<14>_f7 (init_reg_re_reg_mux0031<14>)
  973. LDCP:D -0.071 init_reg.re_reg_14
  974. ----------------------------------------
  975. Total 4.457ns (1.269ns logic, 3.188ns route)
  976. (28.5% logic, 71.5% route)
  977.  
  978. =========================================================================
  979. Timing constraint: Default OFFSET IN BEFORE for Clock 'mclk1'
  980. Total number of paths / destination ports: 9 / 9
  981. -------------------------------------------------------------------------
  982. Offset: 2.345ns (Levels of Logic = 2)
  983. Source: go (PAD)
  984. Destination: i_0 (FF)
  985. Destination Clock: mclk1 rising
  986.  
  987. Data Path: go to i_0
  988. Gate Net
  989. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  990. ---------------------------------------- ------------
  991. IBUF:I->O 3 0.818 0.491 go_IBUF (go_IBUF)
  992. LUT3:I2->O 7 0.094 0.369 i_or00011 (i_or0001)
  993. FDS:S 0.573 i_0
  994. ----------------------------------------
  995. Total 2.345ns (1.485ns logic, 0.860ns route)
  996. (63.3% logic, 36.7% route)
  997.  
  998. =========================================================================
  999. Timing constraint: Default OFFSET IN BEFORE for Clock 'divisor<0>'
  1000. Total number of paths / destination ports: 5515 / 99
  1001. -------------------------------------------------------------------------
  1002. Offset: 7.365ns (Levels of Logic = 9)
  1003. Source: divisor<26> (PAD)
  1004. Destination: init_reg.quo_reg_0 (LATCH)
  1005. Destination Clock: divisor<0> falling
  1006.  
  1007. Data Path: divisor<26> to init_reg.quo_reg_0
  1008. Gate Net
  1009. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  1010. ---------------------------------------- ------------
  1011. IBUF:I->O 68 0.818 0.923 divisor_26_IBUF (divisor_26_IBUF)
  1012. LUT4:I0->O 6 0.094 0.816 shift_val_or0000111 (N344)
  1013. LUT6:I2->O 13 0.094 1.039 init_reg_re_reg_mux0031<22>11 (N61)
  1014. LUT6:I1->O 179 0.094 0.731 init_reg_re_reg_mux0031<13>11 (N46)
  1015. LUT5:I3->O 57 0.094 0.921 init_reg_re_reg_or00011 (init_reg_re_reg_or0001)
  1016. LUT4:I0->O 4 0.094 0.726 init_reg_quo_reg_mux0031<0>41 (N332)
  1017. LUT6:I3->O 1 0.094 0.000 init_reg_quo_reg_mux0031<0>351 (init_reg_quo_reg_mux0031<0>351)
  1018. MUXF7:I1->O 1 0.254 0.480 init_reg_quo_reg_mux0031<0>35_f7 (init_reg_quo_reg_mux0031<0>35)
  1019. LUT6:I5->O 3 0.094 0.000 init_reg_quo_reg_mux0031<0>329 (init_reg_quo_reg_mux0031<0>)
  1020. LDCP:D -0.071 init_reg.quo_reg_0
  1021. ----------------------------------------
  1022. Total 7.365ns (1.730ns logic, 5.635ns route)
  1023. (23.5% logic, 76.5% route)
  1024.  
  1025. =========================================================================
  1026. Timing constraint: Default OFFSET OUT AFTER for Clock 'mclk1'
  1027. Total number of paths / destination ports: 1999462 / 64
  1028. -------------------------------------------------------------------------
  1029. Offset: 12.160ns (Levels of Logic = 54)
  1030. Source: i_re_0 (FF)
  1031. Destination: re<30> (PAD)
  1032. Source Clock: mclk1 rising
  1033.  
  1034. Data Path: i_re_0 to re<30>
  1035. Gate Net
  1036. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  1037. ---------------------------------------- ------------
  1038. FD:C->Q 26 0.471 0.915 i_re_0 (i_re_0)
  1039. LUT4:I0->O 1 0.094 0.000 Mcompar_re_cmp_ge0010_lut<0> (Mcompar_re_cmp_ge0010_lut<0>)
  1040. MUXCY:S->O 1 0.372 0.000 Mcompar_re_cmp_ge0010_cy<0> (Mcompar_re_cmp_ge0010_cy<0>)
  1041. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0010_cy<1> (Mcompar_re_cmp_ge0010_cy<1>)
  1042. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0010_cy<2> (Mcompar_re_cmp_ge0010_cy<2>)
  1043. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0010_cy<3> (Mcompar_re_cmp_ge0010_cy<3>)
  1044. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0010_cy<4> (Mcompar_re_cmp_ge0010_cy<4>)
  1045. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0010_cy<5> (Mcompar_re_cmp_ge0010_cy<5>)
  1046. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0010_cy<6> (Mcompar_re_cmp_ge0010_cy<6>)
  1047. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0010_cy<7> (Mcompar_re_cmp_ge0010_cy<7>)
  1048. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0010_cy<8> (Mcompar_re_cmp_ge0010_cy<8>)
  1049. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0010_cy<9> (Mcompar_re_cmp_ge0010_cy<9>)
  1050. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0010_cy<10> (Mcompar_re_cmp_ge0010_cy<10>)
  1051. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0010_cy<11> (Mcompar_re_cmp_ge0010_cy<11>)
  1052. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0010_cy<12> (Mcompar_re_cmp_ge0010_cy<12>)
  1053. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0010_cy<13> (Mcompar_re_cmp_ge0010_cy<13>)
  1054. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0010_cy<14> (Mcompar_re_cmp_ge0010_cy<14>)
  1055. MUXCY:CI->O 69 0.254 0.844 Mcompar_re_cmp_ge0010_cy<15> (re_cmp_ge0010)
  1056. LUT3:I0->O 61 0.094 1.202 re_mux0000<1>11111 (N517)
  1057. LUT6:I0->O 1 0.094 0.576 re_mux0000<1>81 (re_mux0000<1>81)
  1058. LUT6:I4->O 1 0.094 0.710 re_mux0000<1>150 (re_mux0000<1>150)
  1059. LUT6:I3->O 1 0.094 0.576 re_mux0000<1>209 (re_mux0000<1>)
  1060. LUT3:I1->O 1 0.094 0.000 Maddsub_re_share0000_lut<1> (Maddsub_re_share0000_lut<1>)
  1061. MUXCY:S->O 1 0.372 0.000 Maddsub_re_share0000_cy<1> (Maddsub_re_share0000_cy<1>)
  1062. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<2> (Maddsub_re_share0000_cy<2>)
  1063. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<3> (Maddsub_re_share0000_cy<3>)
  1064. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<4> (Maddsub_re_share0000_cy<4>)
  1065. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<5> (Maddsub_re_share0000_cy<5>)
  1066. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<6> (Maddsub_re_share0000_cy<6>)
  1067. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<7> (Maddsub_re_share0000_cy<7>)
  1068. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<8> (Maddsub_re_share0000_cy<8>)
  1069. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<9> (Maddsub_re_share0000_cy<9>)
  1070. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<10> (Maddsub_re_share0000_cy<10>)
  1071. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<11> (Maddsub_re_share0000_cy<11>)
  1072. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<12> (Maddsub_re_share0000_cy<12>)
  1073. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<13> (Maddsub_re_share0000_cy<13>)
  1074. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<14> (Maddsub_re_share0000_cy<14>)
  1075. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<15> (Maddsub_re_share0000_cy<15>)
  1076. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<16> (Maddsub_re_share0000_cy<16>)
  1077. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<17> (Maddsub_re_share0000_cy<17>)
  1078. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<18> (Maddsub_re_share0000_cy<18>)
  1079. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<19> (Maddsub_re_share0000_cy<19>)
  1080. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<20> (Maddsub_re_share0000_cy<20>)
  1081. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<21> (Maddsub_re_share0000_cy<21>)
  1082. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<22> (Maddsub_re_share0000_cy<22>)
  1083. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<23> (Maddsub_re_share0000_cy<23>)
  1084. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<24> (Maddsub_re_share0000_cy<24>)
  1085. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<25> (Maddsub_re_share0000_cy<25>)
  1086. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<26> (Maddsub_re_share0000_cy<26>)
  1087. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<27> (Maddsub_re_share0000_cy<27>)
  1088. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<28> (Maddsub_re_share0000_cy<28>)
  1089. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<29> (Maddsub_re_share0000_cy<29>)
  1090. XORCY:CI->O 1 0.357 0.973 Maddsub_re_share0000_xor<30> (re_share0000<30>)
  1091. LUT5:I0->O 1 0.094 0.336 re<30>1 (re_30_OBUF)
  1092. OBUF:I->O 2.452 re_30_OBUF (re<30>)
  1093. ----------------------------------------
  1094. Total 12.160ns (6.028ns logic, 6.132ns route)
  1095. (49.6% logic, 50.4% route)
  1096.  
  1097. =========================================================================
  1098. Timing constraint: Default path analysis
  1099. Total number of paths / destination ports: 379116811 / 64
  1100. -------------------------------------------------------------------------
  1101. Delay: 15.580ns (Levels of Logic = 74)
  1102. Source: divisor<1> (PAD)
  1103. Destination: re<30> (PAD)
  1104.  
  1105. Data Path: divisor<1> to re<30>
  1106. Gate Net
  1107. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  1108. ---------------------------------------- ------------
  1109. IBUF:I->O 229 0.818 0.740 divisor_1_IBUF (divisor_1_IBUF)
  1110. LUT2:I0->O 1 0.094 0.000 Mmult_re_mult0008_Madd_lut<1> (Mmult_re_mult0008_Madd_lut<1>)
  1111. MUXCY:S->O 1 0.372 0.000 Mmult_re_mult0008_Madd_cy<1> (Mmult_re_mult0008_Madd_cy<1>)
  1112. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<2> (Mmult_re_mult0008_Madd_cy<2>)
  1113. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<3> (Mmult_re_mult0008_Madd_cy<3>)
  1114. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<4> (Mmult_re_mult0008_Madd_cy<4>)
  1115. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<5> (Mmult_re_mult0008_Madd_cy<5>)
  1116. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<6> (Mmult_re_mult0008_Madd_cy<6>)
  1117. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<7> (Mmult_re_mult0008_Madd_cy<7>)
  1118. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<8> (Mmult_re_mult0008_Madd_cy<8>)
  1119. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<9> (Mmult_re_mult0008_Madd_cy<9>)
  1120. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<10> (Mmult_re_mult0008_Madd_cy<10>)
  1121. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<11> (Mmult_re_mult0008_Madd_cy<11>)
  1122. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<12> (Mmult_re_mult0008_Madd_cy<12>)
  1123. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<13> (Mmult_re_mult0008_Madd_cy<13>)
  1124. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<14> (Mmult_re_mult0008_Madd_cy<14>)
  1125. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<15> (Mmult_re_mult0008_Madd_cy<15>)
  1126. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<16> (Mmult_re_mult0008_Madd_cy<16>)
  1127. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<17> (Mmult_re_mult0008_Madd_cy<17>)
  1128. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<18> (Mmult_re_mult0008_Madd_cy<18>)
  1129. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<19> (Mmult_re_mult0008_Madd_cy<19>)
  1130. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<20> (Mmult_re_mult0008_Madd_cy<20>)
  1131. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<21> (Mmult_re_mult0008_Madd_cy<21>)
  1132. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<22> (Mmult_re_mult0008_Madd_cy<22>)
  1133. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<23> (Mmult_re_mult0008_Madd_cy<23>)
  1134. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<24> (Mmult_re_mult0008_Madd_cy<24>)
  1135. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<25> (Mmult_re_mult0008_Madd_cy<25>)
  1136. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<26> (Mmult_re_mult0008_Madd_cy<26>)
  1137. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<27> (Mmult_re_mult0008_Madd_cy<27>)
  1138. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<28> (Mmult_re_mult0008_Madd_cy<28>)
  1139. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<29> (Mmult_re_mult0008_Madd_cy<29>)
  1140. XORCY:CI->O 1 0.357 0.336 Mmult_re_mult0008_Madd_xor<30> (re_mult0008<30>)
  1141. INV:I->O 1 0.238 0.000 Madd_re_not0001<30>1_INV_0 (Madd_re_not0001<30>)
  1142. MUXCY:S->O 0 0.372 0.000 Madd_re_sub0002_cy<30> (Madd_re_sub0002_cy<30>)
  1143. XORCY:CI->O 2 0.357 0.794 Madd_re_sub0002_xor<31> (re_sub0002<31>)
  1144. LUT4:I0->O 0 0.094 0.000 Mcompar_re_cmp_ge0010_lutdi15 (Mcompar_re_cmp_ge0010_lutdi15)
  1145. MUXCY:DI->O 69 0.590 0.844 Mcompar_re_cmp_ge0010_cy<15> (re_cmp_ge0010)
  1146. LUT3:I0->O 61 0.094 1.202 re_mux0000<1>11111 (N517)
  1147. LUT6:I0->O 1 0.094 0.576 re_mux0000<1>81 (re_mux0000<1>81)
  1148. LUT6:I4->O 1 0.094 0.710 re_mux0000<1>150 (re_mux0000<1>150)
  1149. LUT6:I3->O 1 0.094 0.576 re_mux0000<1>209 (re_mux0000<1>)
  1150. LUT3:I1->O 1 0.094 0.000 Maddsub_re_share0000_lut<1> (Maddsub_re_share0000_lut<1>)
  1151. MUXCY:S->O 1 0.372 0.000 Maddsub_re_share0000_cy<1> (Maddsub_re_share0000_cy<1>)
  1152. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<2> (Maddsub_re_share0000_cy<2>)
  1153. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<3> (Maddsub_re_share0000_cy<3>)
  1154. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<4> (Maddsub_re_share0000_cy<4>)
  1155. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<5> (Maddsub_re_share0000_cy<5>)
  1156. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<6> (Maddsub_re_share0000_cy<6>)
  1157. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<7> (Maddsub_re_share0000_cy<7>)
  1158. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<8> (Maddsub_re_share0000_cy<8>)
  1159. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<9> (Maddsub_re_share0000_cy<9>)
  1160. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<10> (Maddsub_re_share0000_cy<10>)
  1161. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<11> (Maddsub_re_share0000_cy<11>)
  1162. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<12> (Maddsub_re_share0000_cy<12>)
  1163. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<13> (Maddsub_re_share0000_cy<13>)
  1164. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<14> (Maddsub_re_share0000_cy<14>)
  1165. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<15> (Maddsub_re_share0000_cy<15>)
  1166. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<16> (Maddsub_re_share0000_cy<16>)
  1167. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<17> (Maddsub_re_share0000_cy<17>)
  1168. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<18> (Maddsub_re_share0000_cy<18>)
  1169. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<19> (Maddsub_re_share0000_cy<19>)
  1170. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<20> (Maddsub_re_share0000_cy<20>)
  1171. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<21> (Maddsub_re_share0000_cy<21>)
  1172. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<22> (Maddsub_re_share0000_cy<22>)
  1173. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<23> (Maddsub_re_share0000_cy<23>)
  1174. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<24> (Maddsub_re_share0000_cy<24>)
  1175. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<25> (Maddsub_re_share0000_cy<25>)
  1176. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<26> (Maddsub_re_share0000_cy<26>)
  1177. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<27> (Maddsub_re_share0000_cy<27>)
  1178. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<28> (Maddsub_re_share0000_cy<28>)
  1179. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<29> (Maddsub_re_share0000_cy<29>)
  1180. XORCY:CI->O 1 0.357 0.973 Maddsub_re_share0000_xor<30> (re_share0000<30>)
  1181. LUT5:I0->O 1 0.094 0.336 re<30>1 (re_30_OBUF)
  1182. OBUF:I->O 2.452 re_30_OBUF (re<30>)
  1183. ----------------------------------------
  1184. Total 15.580ns (8.493ns logic, 7.087ns route)
  1185. (54.5% logic, 45.5% route)
  1186.  
  1187. =========================================================================
  1188.  
  1189.  
  1190. Total REAL time to Xst completion: 1441.00 secs
  1191. Total CPU time to Xst completion: 1439.51 secs
  1192.  
  1193. -->
  1194.  
  1195.  
  1196. Total memory usage is 651836 kilobytes
  1197.  
  1198. Number of errors : 0 ( 0 filtered)
  1199. Number of warnings : 92 ( 0 filtered)
  1200. Number of infos : 2 ( 0 filtered)
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