SpinalHDL AXI crossbar with 2 SRAM's

package vexriscv.demo


import spinal.core._
import spinal.lib._
import spinal.lib.bus.amba3.apb._
import spinal.lib.bus.amba4.axi._

import spinal.lib.misc.HexTools

import scala.collection.mutable.ArrayBuffer
import scala.collection.Seq

class TinyClunx(
                onChipRamSize : BigInt
                ) extends Component{

    val axiConfig = Axi4Config(
    addressWidth = 17,
    dataWidth    = 64,
    idWidth      = 3,
    useRegion    = false,
    useLock      = false,
    useQos      = false,
    useResp = false,
    useProt=false,
    useStrb=false
        )

  val debug = true

  val io = new Bundle{
    //Clocks / reset
    val axiReset = in Bool()
    val axiClk   = in Bool()
    val axiM1    = slave(Axi4(axiConfig))
    val axiM2    = slave(Axi4(axiConfig))
    //val axiM1    = slave(Axi4Shared(axiConfig))
    //val axiM2    = slave(Axi4Shared(axiConfig))
  }

  val axiClockDomain = ClockDomain(
    clock = io.axiClk,
    reset = io.axiReset
    )

  val axi1 = new ClockingArea(axiClockDomain) {
    val ram1 = Axi4SharedOnChipRam(
      dataWidth = 64,
      byteCount = onChipRamSize,
      idWidth = axiConfig.idWidth+1
    )

    val ram2 = Axi4SharedOnChipRam(
      dataWidth = 64,
      byteCount = onChipRamSize,
      idWidth = axiConfig.idWidth+1
    )

    val axiCrossbar = Axi4CrossbarFactory()

    axiCrossbar.addSlaves(
      ram1.io.axi       -> (0x00000000L,   onChipRamSize),
      ram2.io.axi       -> (0x00010000L,   onChipRamSize)
    )

    axiCrossbar.addConnections(
      io.axiM2        -> List(ram1.io.axi, ram2.io.axi),
      io.axiM1        -> List(ram1.io.axi, ram2.io.axi)
    )


    axiCrossbar.build()

  }

}

object TinyClunx{
  def main(args: Array[String]) {
    val config = SpinalConfig()
    config.generateVerilog({
      val toplevel = new TinyClunx(onChipRamSize = 8 kB)
      toplevel
    })
  }
}

// With memory init
object TinyCClunxWithMemoryInit{
  def main(args: Array[String]) {
    val config = SpinalConfig()
    config.generateVerilog({
      val toplevel = new TinyClunx(onChipRamSize = 8 kB)
      HexTools.initRam(toplevel.axi1.ram1.ram, "src/main/ressource/hex/muraxDemo.hex", 0x80000000l)
      toplevel
    })
  }
}