funkcijaLabos

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- warning: this file will not be saved if:
--     * following entity block contains any syntactic errors (e.g. port list isn't separated with ; character)
--     * following entity name and current file name differ (e.g. if file is named mux41 then entity must also be named mux41 and vice versa)
ENTITY funkcijaLabos IS PORT(
    a: IN std_logic;
    b: IN std_logic;
    c: IN std_logic;
    f: OUT std_logic
);
END funkcijaLabos;

ARCHITECTURE arch OF funkcijaLabos IS
    signal tmp1: std_logic;
    signal tmp20, tmp21, tmp22: std_logic;
    signal tmp3: std_logic_vector(0 to 7);

BEGIN
    tmp1 <= '1';
    tmp20 <= a;
    tmp21 <= b;
    tmp22 <= c;

    d1: entity work.dekoder38 port map(tmp1, tmp20, tmp21, tmp22, tmp3);

    f <= tmp3(2) or tmp3(3) or tmp3(5);

END arch;