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- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_unsigned.all;
- entity zadatakB_tb is
- end entity;
- architecture Test of zadatakB_tb is
- --Inputs and outputs
- signal sCLK : std_logic := '0';
- signal sRST : std_logic := '0';
- signal sEN : std_logic := '0';
- signal sDATA : std_logic_vector(7 downto 0);
- signal sLOAD : std_logic;
- signal sCODE : std_logic_vector(2 downto 0);
- signal sCNTG : std_logic_vector(3 downto 0);
- signal sCNTS : std_logic_vector(3 downto 0);
- constant iCLK_PERIOD : time := 10 ns;
- component zadatakB is port(
- iCLK : in std_logic;
- iRST : in std_logic;
- iEN : in std_logic;
- iDATA : in std_logic_vector(7 downto 0);
- iLOAD : in std_logic;
- oCODE : out std_logic_vector(2 downto 0);
- oCNTG : out std_logic_vector(3 downto 0);
- oCNTS : out std_logic_vector(3 downto 0)
- );
- end component;
- begin
- uut: zadatakB port map (
- iCLK => sCLK,
- iRST => sRST,
- iEN => sEN,
- iDATA => sDATA,
- iLOAD => sLOAD,
- oCODE => sCODE,
- oCNTG => sCNTG,
- oCNTS => sCNTS
- );
- --takt process
- clk_proc : process
- begin
- sCLK <= '1';
- wait for iCLK_PERIOD / 2;
- sCLK <= '0';
- wait for iCLK_PERIOD / 2;
- end process;
- -- Stimulus process
- stim_proc: process
- begin
- --Resetovati sistem tačno 3.25 perioda takta
- sRST <= '1';
- wait for 3.25 * iCLK_PERIOD;
- sRST <= '0';
- --Postaviti na ulaz komplementera takvu vrednost da u rotirajućem registru završi broj 2
- sDATA <= "11111110";
- sLOAD <= '1';
- wait for iCLK_PERIOD;
- sLOAD <= '0';
- --Dati dozvolu rotirajućem registru sve dok vrednost u registru ne postane veća od 5
- --i onda ukinuti dozvolu dok brojač većih ne izbroji do 10
- sEN <= '1';
- wait for 2 * iCLK_PERIOD;
- sEN <= '0';
- wait for 10 * iCLK_PERIOD;
- --Potom dati dozvolu za rad rotirajućem registru sve dok vrednost u njemu ne bude manja od 5
- --i onda ukinuti dozvolu dok brojač manjih ne izbroji do 5
- sEN <= '1';
- wait for 5 * iCLK_PERIOD;
- sEN <= '0';
- wait for 2 * iCLK_PERIOD;
- --Resetovati sistem
- sRST <= '1';
- wait;
- end process;
- end architecture;
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