question_11

// Code your design here

//Interface

interface ifc(input clk);
  logic rst;
  logic coin;
  logic dwash;
  logic lid;
  logic soak;
  logic wash;
  logic rinse;
  logic spin;
  logic done;

  modport DESIGN(
    input clk, rst, coin, dwash, lid,
    output soak, wash, rinse, spin, done
  );

  modport TEST(
    output rst, coin, dwash, lid,
    input soak, wash, rinse, spin, done, clk
  );
endinterface

// Controller

module wmc(
  ifc.DESIGN inf,
  input T,
  output pause
);

  reg [2:0] nst, cst;
  localparam [2:0]
  IDLE = 0,
  SOAK = 1,
  WASH = 2,
  RINSE = 3,
  SPIN = 4,
  DWASH = 5,
  DRINSE = 6,
  PAUSE = 7;
  always@(posedge inf.clk or negedge inf.rst) begin
    if(!inf.rst) cst <= IDLE;
    else cst <= nst;
  end

  always_comb begin
    nst <= cst;
    case(cst)
      IDLE: if(inf.coin) nst <= SOAK;
      SOAK: if(T) nst <= WASH;
      WASH: if(T) nst <= RINSE;
      RINSE: begin
        if(inf.dwash & T) nst <= DWASH;
        else if(!inf.dwash & T) nst <= SPIN;
      end
      SPIN: begin
        if(inf.lid & !T) nst <= PAUSE;
        else if(T) nst <= IDLE;
      end
      DWASH: if(T) nst <= DRINSE;
      DRINSE: if(T) nst <= SPIN;
      PAUSE: if(!inf.lid) nst <= SPIN;
    endcase
  end

  assign inf.soak = (cst == SOAK);
  assign inf.wash = (cst == WASH) | (cst == DWASH);
  assign inf.rinse = (cst == RINSE) | (cst == DRINSE);
  assign inf.spin = (cst == SPIN);
  assign pause = (cst == PAUSE);
  assign inf.done = (cst == IDLE);
endmodule

// Timer

module timer(
  input clk, rst, pause,
  output T
);

  reg [9:0] count;

  always@(posedge clk or negedge rst) begin
    if(!rst) count <= 10'd0;
    else if(pause) count<= count;
    else count <= count + 1'b1;
  end

  assign T = (&count);
endmodule


// Top Level Controller

module washing_machine(
  ifc.DESIGN inf
);
  wire pause, T;
  wmc W1(.inf(inf), .T(T), .pause(pause));
  timer T1(.clk(inf.clk), .rst(inf.rst), .pause(pause), .T(T));

endmodule







///////////////////////program block


// Code your testbench here
// or browse Examples
program tb_washing_machine(
  ifc.TEST inf
);

  virtual ifc.TEST inf_h = inf;

  initial begin
    inf_h.rst = 0;
    #12 inf_h.rst = 1;
  end

  initial begin
    wait(inf_h.rst);
    inf_h.coin = 1'b1;
    inf_h.dwash = 1'b1;

    #10 inf_h.coin = 1'b0;

    wait(inf_h.spin);
    inf_h.lid = 1'b1;
    #24 inf_h.lid = 1'b0;

    wait(inf_h.done);
    $finish;

  end

  initial begin
    $dumpfile("dump.vcd");
    $dumpvars;
  end
endprogram

module top_washing_machine;

  reg clk;
  ifc inf(clk);
  washing_machine DUT(.inf(inf.DESIGN));
  tb_washing_machine TEST(.inf(inf.TEST));

  initial begin
    wait(inf.rst);
    clk = 0;
    forever #5 clk = ~clk;
  end

endmodule