TBA

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity zadatakA_tb is
end entity;

architecture Test of zadatakA_tb is

    --Inputs and outputs
   signal sCLK   : std_logic := '0';
   signal sRST   : std_logic := '0';
   signal sEN    : std_logic := '0';
    signal sDEC   : std_logic_vector(2 downto 0);
    signal sGREAT    : std_logic;
    signal sCNTP   : std_logic_vector(3 downto 0);
    signal sCNTN   : std_logic_vector(3 downto 0);

    constant iCLK_PERIOD : time := 10 ns;

   component zadatakA is port(
            iCLK    : in  std_logic;
         iRST    : in  std_logic;
         iEN     : in  std_logic;
            iDEC     : in std_logic_vector(2 downto 0);
            oGREAT   : out std_logic;
            oCNTP   : out std_logic_vector(3 downto 0);
            oCNTN   : out std_logic_vector(3 downto 0)
      );
   end component;

begin

   uut: zadatakA port map (
          iCLK => sCLK,
          iRST => sRST,
          iEN => sEN,
             iDEC => sDEC,
             oGREAT => sGREAT,
             oCNTP => sCNTP,
             oCNTN => sCNTN
        );

    --takt process
    clk_proc : process
    begin
        sCLK <= '1';
        wait for iCLK_PERIOD / 2;
        sCLK <= '0';
        wait for iCLK_PERIOD / 2;
    end process;

   -- Stimulus process
   stim_proc: process
   begin

        sDEC <= "000";--da ne bude crveno na pocetku
        sRST <= '1';
        wait for 5.25 * iCLK_PERIOD;
        sRST <= '0';
        --Postaviti na ulaz dekodera takvu vrednost da brojač neparnih brojeva izbroji do 10
        sDEC <= "000";
        sEN <= '1';
        wait for iCLK_PERIOD;
        sEN <= '0';
        wait for 9 * iCLK_PERIOD;
        --Postaviti na ulaz dekodera takvu vrednost da brojač parnih brojeva izbroji do 8
        sDEC <= "010";
        sEN <= '1';
        wait for iCLK_PERIOD;
        sEN <= '0';
        wait for 8 * iCLK_PERIOD;
        --Resetovati sistem na 5 perioda takta
        sRST <= '1';
        wait for 5 * iCLK_PERIOD;
        sRST <= '0';
        ----Postaviti na ulaz dekodera takvu vrednost da izlaz iz komparatora bude ‘1’ 10 perioda takta
        sEN <= '1';
        sDEC <= "111";
        wait for iCLK_PERIOD;
        sEN <= '0';
        wait for 9 * iCLK_PERIOD;
        ----Postaviti na ulaz dekodera takvu vrednost da izlaz iz komparatora bude ‘0’ 10 perioda takta
        sDEC <= "010";
        sEN <= '1';
        wait for iCLK_PERIOD;
        sEN <= '0';
        wait for 9 * iCLK_PERIOD;
        ----Resetovati sistem
        sRST <= '1';

        wait;
   end process;

end architecture;