modelsim

# command chain to force
force A 0
force B 0
run
force B 1
run
force A 1
force B 0
run
force B 1
run

# test bench
library IEEE;
use IEEE.std_logic_1164.all;

entity gate_tb is
end entity gate_tb;

architecture test of gate_tb is
        component []
          port (
                A : in std_logic;
                B : in std_logic;
                Y  : out std_logic);
        end component;

        signal A, B, O : std_logic;
begin
        gate_map: [] port map (A => A, B => B, Y => O);

        process begin
                A <= '0';
                B <= '0';
                wait for 100 ps;

                A <= '0';
                B <= '1';
                wait for 100 ps;

                A <= '1';
                B <= '0';
                wait for 100 ps;

                A <= '1';
                B <= '1';
                wait for 100 ps;
        end process;

end test;