I2S_transmitter

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02/26/2024 09:38:28 AM
// Design Name:
// Module Name: I2S_transmitter
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
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// Dependencies:
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// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

//I2S transmitter: clk = bclk!
module I2S_transmitter
(
    input wire clk,
    input wire rstn,
    output wire lrclk,
    output wire bclk,
    output wire sdo
);

//Copy the input clk to clk
assign bclk = clk;

//Generate rlclk
reg [4:0] cntr;
always @ (negedge clk)
begin
    if(rstn == 1'b0)
        cntr <= 5'd0;
    else
        cntr <= cntr + 1;
end

reg lrclk_reg;
always @ (negedge clk)
begin
    if(rstn == 1'b0)
        lrclk_reg <= 1'b0;
    else if (cntr == 5'd31)
        lrclk_reg <= ~lrclk_reg;
end
assign lrclk = lrclk_reg;

//Shift out data
reg [31:0] ldata;
reg [31:0] rdata;
always @ (negedge clk)
begin
    if((rstn == 1'b0) || (cntr == 5'd31))
    begin
        ldata <= 32'h00fb5210;
        rdata <= 32'h00279ade;
    end
    else if (lrclk_reg == 1'b1)
        ldata <= {ldata[30:0], 1'b0};
    else
        rdata <= {rdata[30:0], 1'b0};
end
assign sdo = (lrclk_reg == 1'b1) ? ldata[31] : rdata[31];

endmodule