LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity FSM_DMA_C is
port (                         -- r_ - register
    clk         :IN     std_logic;
    r_ready         :IN std_logic; -- 0 ничё не меняется
    r_towork_request    :IN     std_logic;
    r_reset         :IN     std_logic;
    r_command_address   :IN std_logic_vector (0 to 15);
    r_data_in       :IN std_logic_vector (0 to 63);
    r_cs            :OUT    std_logic; --+
    r_address_out       :OUT    std_logic_vector (0 to 15);
    r_data_out      :OUT    std_logic_vector (0 to 63);
    r_command       :OUT    std_logic_vector (0 to 1); -- 01 read , 10 - write
    r_output        :OUT    std_logic_vector (0 to 2));
    end FSM_DMA_C;

architecture FSM of FSM_DMA_C IS
    TYPE state_type IS (Idle,Req_Read_INFO_CPU,Req_Read_Com,Read_Com,Req_Read_Info,Read_Info, Write_Info); -- Req - request

    signal state            : state_type; --+
    signal r_buff_data      : std_logic_vector (0 to 63);
    signal r_memo_addr_data     : std_logic_vector (0 to 15);
    signal r_memo_com       : std_logic_vector (0 to 63);
    signal count            : std_logic_vector (0 to 11);
    signal r_buff_address_rd    : std_logic_vector (0 to 15);
    signal r_buff_address_wr    : std_logic_vector (0 to 15);

    begin
    state_proc:
    process (clk)
    begin
    IF r_reset = '1' then
        state <= Idle;
    ELSIF (rising_edge(clk)) then
        IF (r_ready = '1') then
        state <= state;
        else
            CASE state is
                when Idle =>
                    IF (r_towork_request = '1') then
                        state <= Req_Read_INFO_CPU;
                    else
                        state <= Idle;
                    end if;

                when Req_Read_INFO_CPU =>
                    state <= Req_Read_Com;

                when Req_Read_Com =>
                    state <= Read_Com;

                when Read_Com =>
                    state <= Req_Read_Info;

                when Req_Read_Info =>
                    state <= Read_Info;

                when Read_Info =>
                    state <= Write_Info;

                when Write_Info =>
                    if (count = x"000") then
                        if r_memo_com(44) = '1' then -- следующая команда
                                state <= Req_Read_Com;
                        else
                            state <= Idle;
                        end if;
                    else
                        state <= Req_Read_Info;
                    end if;
            end case;   end if;
    end if;
    end process;


proces_sig:
Process (state)
begin
    -------------------------------------in_sig----------------------------------------------
    ----------------------------------r_memo_addr_data-----------------------------------------
    IF (r_ready = '1') then
        r_memo_addr_data<= r_memo_addr_data;
    else
    IF (state = Req_Read_INFO_CPU) then
            r_memo_addr_data <= r_command_address ;
    elsif (state = Write_Info) then
                 if (count = x"000") then
            if r_memo_com(44) = '1' then -- следующая команда
                r_memo_addr_data <= r_memo_com(48 to 63);
            end if;
        else
            r_memo_addr_data<= r_memo_addr_data;
        end if;
    elsif( state = Req_Read_Com or state = Read_Com or state =  Req_Read_Info or state = Read_Info ) then
        r_memo_addr_data <= r_memo_addr_data;

    elsif (state =  Idle ) then
        r_memo_addr_data <= x"0000";
    end if;
    end if;


    -------------------------------------r_buff_data---------------------------------------

    IF (r_ready = '1') then
        r_buff_data <= r_buff_data;
    else
    IF ( state =  Req_Read_Com or state = Req_Read_INFO_CPU or state = Read_Com
    or state = Req_Read_Info or state = Write_Info) then
        r_buff_data <= r_buff_data;
    elsif (state = Read_Info) then
        r_buff_data <= r_data_in;
    elsif (state = Idle) then
        r_buff_data <= x"0000000000000000";
    end if;
    end if;


    ----------------------------------r_memo_com-----------------------------------------
    IF (r_ready = '1') then
        r_memo_com <= r_memo_com;
    else
    IF (state = Req_Read_Com or state = Req_Read_INFO_CPU or state = Req_Read_Info or state = Read_Info or state = Write_Info) then
        r_memo_com <= r_memo_com;
    elsif (state = Read_Com) then
        r_memo_com <= r_data_in;
    elsif (state = Idle) then
        r_memo_com <= x"0000000000000000";
    end if;
    end if;


    ----------------------------------r_count-------------------------------------------
    IF (r_ready = '1') then
        count <= count;
    else
        if (state = Idle or state = Req_Read_Com) then
            count <= x"000";
        elsif (state = Req_Read_INFO_CPU  or state = Read_Info or state = Write_Info or state = Read_Com) then
            count <= count;
        elsif (state = Req_Read_Info) then
            if (count = x"000") then
            count <= r_memo_com(32 to 43);
        else
            count <= count - 1;
        end if;
    end if;
    end if;


    -------------------------------r_buff_address_rd----------------------------------------
    IF (r_ready = '1') then
        r_buff_address_rd <= r_buff_address_rd;
    else
        if (state = Idle) then
            r_buff_address_rd <= x"0000";
        elsif (state = Req_Read_Com or state = Req_Read_INFO_CPU or state = Write_Info or state = Read_Com) then
            r_buff_address_rd <= r_buff_address_rd;
        elsif (state = Req_Read_Info) then
            if count = x"000" then
                r_buff_address_rd <= r_memo_com(0 to 15);
            else
                r_buff_address_rd <= r_buff_address_rd;
            end if;
        elsif (state = Read_Info) then
            r_buff_address_rd <= r_buff_address_rd + '1';
    end if;
    end if;


    -------------------------------r_buff_adress_wr----------------------------------------
    IF (r_ready = '1') then
        r_buff_address_wr <= r_buff_address_wr;
    else
        if (state = Idle) then
            r_buff_address_wr <= x"0000";
    elsif (state = Req_Read_Com or state = Req_Read_INFO_CPU  or state = Read_Info or state = Write_Info or state = Read_Com) then
            r_buff_address_wr <= r_buff_address_wr;
        elsif (state = Req_Read_Info) then
            if count = x"000" then
            r_buff_address_wr <= r_memo_com(16 to 31);
        else
            r_buff_address_wr <= r_buff_address_wr + '1';
        end if;
    end if;
    end if;
    -------------------------------------out_sig-----------------------------------------
    ---------------------------------------r_csl-------------------------------------------
    IF (state = Idle or state = Req_Read_INFO_CPU) then --or state = Read_Com or state = Read_Info) then
        r_cs <= '1';
    elsif (state = Req_Read_Com or state = Req_Read_Com or state = Write_Info or state = Read_Com or state = Read_Info) then
        r_cs <= '0';
    end if;

    ------------------------------------r_comand------------------------------------------
    if r_ready = '1' then
        r_command <= "00";
    else
    IF (state = Req_Read_Com or state = Req_Read_Info) then
        r_command <= "01";
    elsif (state = Write_Info) then
        r_command <= "10";
    elsif (state = Idle or state = Read_Com or state = Req_Read_INFO_CPU or state = Read_Info) then
        r_command <= "00";
    end if;
    end if;


    ------------------------------------r_data_out------------------------------------------
    IF (r_ready = '1') then
        r_data_out <= x"0000000000000000";
    else
    IF (state = Write_Info) then
        r_data_out <= r_buff_data;
    elsif(state = Idle or  state = Req_Read_INFO_CPU or state =  Req_Read_Com or state = Read_Com or state =  Req_Read_Info or state = Read_Info) then
        r_data_out <= x"0000000000000000";
    end if;
    end if;


    ------------------------------------r_adress_out--------------------------------------------
    IF (r_ready = '1') then
        r_address_out <= x"0000";
    else
    IF (state = Idle or state = Req_Read_INFO_CPU or state = Read_Com or state = Read_Info) then
        r_address_out <= x"0000";
    elsif (state = Req_Read_Com) then
        r_address_out <= r_memo_addr_data;
    elsif (state =  Req_Read_Info ) then
        if (count = x"000") then
            r_address_out <= r_memo_com(0 to 15);
        else
            r_address_out <= r_buff_address_rd;
        end if;
    elsif (state = Write_Info) then
        r_address_out <= r_buff_address_wr;
    end if;
    end if;

    -------------------------------------------------------------------------------------------------------

end process;







out_proces_state:
PROCESS (state)
begin
    case state is
        when Idle =>
            r_output <= "000";
        when Req_Read_INFO_CPU =>
            r_output <= "001";
        when Req_Read_Com =>
            r_output <= "010";
        when Read_Com =>
            r_output <= "011";
        when Req_Read_Info =>
            r_output <= "100";
        when Read_Info =>
            r_output <= "101";
        when Write_Info =>
            r_output <= "110";
        end case;
end process;







end FSM;