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ForcaDz

moving

Nov 17th, 2023
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VHDL 0.61 KB | None | 0 0
  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3.  
  4. entity Moving_Colors is
  5.     port (
  6.     Clk100,Reset : in std_logic ;
  7.  
  8.     RED_Out, BLUE_Out, GREEN_Out: out std_logic_vector(3 downto 0));                        
  9. end Moving_Colors;
  10.  
  11.  
  12.  
  13. architecture Behavioral of Moving_Colors is
  14. signal    Clk10 :  std_logic;
  15. begin
  16.  
  17.     -- Diviseur Horloge 100 MHz --> 10 Mhz
  18.     Diviseur:   entity work.ClkDivMC
  19.                 port map(Clk100,Reset,Clk10);
  20.     -- Machine a Etat + Compteurs
  21.     MAE :   entity work.MAE
  22.                 port map(Clk100,Reset,Clk10,RED_Out,BLUE_Out,GREEN_Out);      
  23.    
  24.  
  25. end Behavioral;
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