VHDL HEX

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-- Company:
-- Engineer:
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-- Create Date: 05.10.2016 13:52:49
-- Design Name:
-- Module Name: simula1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
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-- Dependencies:
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-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity simula1 is
    Port( HEX1, HEX2, HEX3, HEX4 : in STD_LOGIC_VECTOR (3 downto 0);
          SEG : out STD_LOGIC_VECTOR (0 to 6);
          an : out STD_LOGIC);
end simula1;

architecture Behavioral of simula1 is

begin
    with HEX select
     SEG <= "0000001" when "0000",
            "1001111" when "0001",
            "0010010" when "0010",
            "0000110" when "0011",
            "1001100" when "0100",
            "0100100" when "0101",
            "0100000" when "0110",
            "0001111" when "0111",
            "0000000" when "1000",
            "0000100" when "1001",
            "1111111" when OTHERS;
end Behavioral;