counter

`timescale 1ns / 1ps

module counter(clk, rst, en, count);
    input clk, rst, en;
    output reg[31:0] count = 0;

    always@ (posedge clk or posedge rst) begin
        if (rst) begin
             count <=0;
        end else if (en) begin
            count <= count +1;
        end
    end
endmodule