`define INIT 3'b000
`define C05 3'b001
`define C10 3'b010
`define C15 3'b011
`define C20 3'b100
`define ExpR 3'b101
`define ExpL 3'b110
`define Cap 3'b111


module fsm_coffee(
input clk, rst,
input credit05, credit10,
input [1:0] coffee,
output [2:0] current_state,
output reg exprr, expr_l, capp);

reg [2:0] state_nxt, state_reg;

always @(posedge clk or negedge rst)
begin
if (~rst)
    state_reg <= 0;
else
    state_reg <= state_nxt;
end

always @(state_reg, coffee, credit05, credit10)
begin
state_nxt = state_reg;
exprr = 0;
expr_l = 0;
capp = 0;

case (state_reg)
`INIT : begin
    if(credit05)
	state_nxt = `C05;
    else if(credit10)
	state_nxt = `C10;
end

`C05: begin
    if(credit05)
	state_nxt = `C10;
    else if(credit10)
	state_nxt = `C15;
end

`C10: begin
    if(credit05)
	state_nxt = `C15;
    else if(credit10)
	state_nxt = `C20;
end

`C15: begin
    if(credit05 || credit10)
	state_nxt = `C20;
end

`C20: begin
    if(coffee==2'b01)
	state_nxt = `ExpR;
	//daca adaugam aici exprr=1 era mealy si dispareau ultimele cazuri
    if(coffee==2'b10)
	state_nxt = `ExpL;
    if(coffee==2'b11)
	state_nxt = `Cap;
end

`ExpR: begin
    state_nxt = `INIT;
    exprr = 1;
end

`ExpL: begin
    state_nxt = `INIT;
    expr_l = 1;
end

`Cap: begin
    state_nxt = `INIT;
    capp = 1;
end

endcase

end

assign current_state = state_reg;

endmodule