counter_tb

`timescale 1ns / 1ps

module counter_tb;

reg clock, reset, enable;
wire[31:0] cnt_out;

counter cnt(
    .clk (clock),
    .rst (reset),
    .count (cnt_out),
    .en (enable)
);

integer i;
initial begin
   i = 0;
    enable = 1;
    clock = 1;
    reset = 1;
    #5 reset = 0;
    for (i = 0 ; i < 32 ; i = i + 1) begin
        #5 clock = ~clock;
        #5 clock = ~clock;
    end
        i = 0;
        enable = 0;
    for (i = 0 ; i < 32 ; i = i + 1) begin
        #5 clock = ~clock;
        #5 clock = ~clock;
    end

    reset = 1;
    #5 clock = ~clock;
    enable = 0;
    #5 enable = 1;
    #5 clock = ~clock;
    for (i = 47 ; i < 56 ; i = i + 1) begin
        #5 clock = ~clock;
        #5 clock = ~clock;
    end
    $stop;
end

endmodule