-- Vhdl test bench created from schematic E:\RA153-2011\Dvobitnisabirac\Dvobitni_sabirac_sch.sch - Mon Nov 05 01:03:55 2012
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "Source->Add"
-- menu in Project Navigator to import the testbench. Then
-- edit the user defined section below, adding code to generate the
-- stimulus for your design.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY Dvobitni_sabirac_sch_Dvobitni_sabirac_sch_sch_tb IS
END Dvobitni_sabirac_sch_Dvobitni_sabirac_sch_sch_tb;
ARCHITECTURE behavioral OF Dvobitni_sabirac_sch_Dvobitni_sabirac_sch_sch_tb IS

   COMPONENT Dvobitni_sabirac_sch
   PORT( iA0    :   IN  STD_LOGIC;
          iB0   :   IN  STD_LOGIC;
          oS0   :   OUT STD_LOGIC;
          oC    :   OUT STD_LOGIC;
          iA1   :   IN  STD_LOGIC;
          iB1   :   IN  STD_LOGIC;
          oS1   :   OUT STD_LOGIC);
   END COMPONENT;

   SIGNAL iA0   :   STD_LOGIC;
   SIGNAL iB0   :   STD_LOGIC;
   SIGNAL oS0   :   STD_LOGIC;
   SIGNAL oC    :   STD_LOGIC;
   SIGNAL iA1   :   STD_LOGIC;
   SIGNAL iB1   :   STD_LOGIC;
   SIGNAL oS1   :   STD_LOGIC;

BEGIN

   UUT: Dvobitni_sabirac_sch PORT MAP(
        iA0 => iA0,
        iB0 => iB0,
        oS0 => oS0,
        oC => oC,
        iA1 => iA1,
        iB1 => iB1,
        oS1 => oS1
   );

-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN
    iA0 <= '1';
    iB0 <= '0';
    iA1 <= '1';
    iB1 <= '1';
    wait for 50 ns;
    iA0 <= '0';
    iB0 <= '1';
    iA1 <='1';
    iB1 <= '1';
    wait for 50 ns;
    iA0 <= '1';
    iB0 <= '1';
    iA1 <='0';
    iB1 <= '0';
    wait for 50 ns;
    iA0 <= '1';
    iB0 <= '1';
    iA1 <= '0';
    iB1 <= '1';
    wait for 50 ns;
    iA0 <= '1';
    iB0 <= '1';
    iA1 <= '0';
    iB1 <= '1';
    wait for 50 ns;
    iA0 <= '1';
    iB0 <= '1';
    iA1 <= '1';
    iB1 <= '1';
    wait for 50 ns;
      WAIT; -- will wait forever
   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;


----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    01:16:53 11/05/2012
-- Design Name:
-- Module Name:    cetvorobitnisabirac_vhdl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cetvorobitni_sabirac is
    Port ( iA : in  STD_LOGIC_VECTOR (3 downto 0);
           iB : in  STD_LOGIC_VECTOR (3 downto 0);
           oLED : out  STD_LOGIC_VECTOR (7 downto 0);
              iJOY : in STD_LOGIC_VECTOR (4 downto 0)
);

end cetvorobitni_sabirac;

architecture Behavioral of cetvorobitni_sabirac is
    SIGNAL oS: STD_LOGIC_VECTOR (3 downto 0);
    SIGNAL oC: STD_LOGIC_VECTOR (3 downto 0);
    SIGNAL oLED1 : STD_LOGIC_VECTOR (7 downto 0); -- Led1 izlaz za plocu
    SIGNAL oLED2 : STD_LOGIC_VECTOR (7 downto 0); -- Led2 izlaz za plocu


begin
-- Prvi potpuni sabirac
    oC(0) <= (iA(0) and iB(0)) or (iA(0) and '0') or (iB(0) and '0');
    oS(0) <= iA(0) xor iB(0) xor '0';

-- Drugi potpuni sabirac
    oC(1) <= (iA(1) and iB(1)) or (iA(1) and oC(0)) or (iB(1) and oC(0));
    oS(1) <= iA(1) xor iB(1) xor oC(0);

-- Treci potpuni sabirac
    oC(2) <= (iA(2) and iB(2)) or (iA(2) and oC(1)) or (iB(2) and oC(1));
    oS(2) <= iA(2) xor iB(2) xor oC(1);

-- Cetvrti potpuni sabirac
    oC(3) <= (iA(3) and iB(3)) or (iA(3) and oC(2)) or (iB(3) and oC(2));
    oS(3) <= iA(3) xor iB(3) xor oC(2);

-- Ukupna suma
    oLED1 <= ("000"&oC(3)&oS);

-- Prvi dodatak
    oLED2 <= ("000"&oC(3)&oS) when iJOY = "11111" else
                "00010001" when iJOY="01110" else
                "00100010" when iJOY="01101" else
                "01000100" when iJOY="01011" else
                "10001000" when iJOY="00111" else
                "11111111";

-- Drugi dodatak
process(iA, iB, iJOY, oLED1, oLED2)
begin
    case (iA(1 downto 0)) is
        when "00" => oLED <= oLED1;
        when "01" => oLED <= oLED2;
        when "10" => oLED <= iB&iA;
        when "11" => oLED <= ("0000000" & (iA(0) xor iA(1) xor iA(2) xor iA(3) xor iB(0) xor iB(1) xor iB(2) xor iB(3)));
        when others  => oLED <= "11111111";
    end case;
end process;

-- Treci dodatak

end Behavioral;