`timescale 1ns / 1ps

module Execute #(
    parameter p_data_width = 16
)(
    output [p_data_width-1:0] out_t1, // ALU output
    input [p_data_width-1:0] i_ir, // RI code
    input [p_data_width-1:0] i_t1, // T1 value
    input [p_data_width-1:0] i_t2, // T2 value
    input i_w_clk, // Clock
    input i_w_reset, // Reset
    input i_w_write_t1, // T1 Write Enable
    input i_w_write_t2, // T2 Write Enable
    input i_w_carry // Carry
    );

    localparam ADC  = 4'd0;
    localparam AND  = 4'd1;
    localparam OR   = 4'd2;
    localparam SHL  = 4'd3;
    localparam SHR  = 4'd4;
    localparam SAR  = 4'd5;

    wire l_w_t1_we;
    wire l_w_t1_oe;
    wire [p_data_width-1:0] l_w_t1_out;

    register #(.p_data_width(p_data_width)) instanta_t1(
        .o_w_out(l_w_t1_out),
        .i_w_clk(i_w_clk),
        .i_w_reset(i_w_reset),
        .i_w_in(i_t1),
        .i_w_we(l_w_t1_we),
        .i_w_oe(l_w_t1_oe)
    );

    wire l_w_t2_we;
    wire l_w_t2_oe;
    wire [p_data_width-1:0] l_w_t2_out;

    register #(.p_data_width(p_data_width)) instanta_t2(
        .o_w_out(l_w_t2_out),
        .i_w_clk(i_w_clk),
        .i_w_reset(i_w_reset),
        .i_w_in(i_t2),
        .i_w_we(l_w_t2_we),
        .i_w_oe(l_w_t2_oe)
    );

    wire [3:0] l_w_opcode;
    wire l_w_alu_oe;

    ALU alu(
    .o_w_out(out_t1),
    .i_w_in1(l_w_t1_out),
    .i_w_in2(l_w_t2_out),
    .i_w_opcode(l_w_opcode),
    .i_w_carry(i_w_carry),
    .i_w_oe(l_w_alu_oe)
    );

    localparam STATE_INITIAL = 3'd0;
    localparam STATE_T1_WRITE = 3'd1;
    localparam STATE_T2_WRITE = 3'd2;
    localparam STATE_T_OUT = 3'd3;
    localparam STATE_ALU_EXEC = 3'd4;
    localparam STATE_ALU_OUT = 3'd5;
    localparam STATE_RESTART = 3'd6;

    reg [2:0] l_r_state;
    reg [2:0] l_r_next_state;

    // Sequential block
    always @(posedge i_w_clk) begin
        if(i_w_reset == 1'b0) begin
            l_r_state <= STATE_INITIAL;
        end else begin
            l_r_state <= l_r_next_state;
        end
    end

    // Auxiliary reg variables
    reg l_r_t1_we;
    reg l_r_t1_oe;
    reg l_r_t2_we;
    reg l_r_t2_oe;
    reg [3:0] l_r_opcode;
    reg l_r_alu_oe;

    // Combinational block
    always @(*) begin
        case(l_r_state)
            // Initial state
            STATE_INITIAL:
                if (i_w_write_t1) begin
                    l_r_next_state = STATE_T1_WRITE;
                end
                else begin
                    l_r_next_state = STATE_INITIAL;
                end
            // Input value is written into T1
            STATE_T1_WRITE: begin
                l_r_t1_we = 1;
                // Verify the number of operands
                if (i_ir[1] == 1) begin
                    if (i_w_write_t2) begin
                        l_r_next_state = STATE_T2_WRITE;
                     end
                     else begin
                        l_r_next_state = STATE_T1_WRITE;
                     end
                 end
                 else begin
                    l_r_next_state = STATE_T_OUT;
                 end
             end
             // [Optional] Input value is written into T2
             STATE_T2_WRITE: begin
                l_r_t2_we = 1;
                l_r_next_state = STATE_T_OUT;
             end
             // T1 and T2 output signals are enabled
             STATE_T_OUT: begin
                l_r_t1_oe = 1;
                l_r_t2_oe = 1;
                l_r_next_state = STATE_ALU_EXEC;
             end
             // T1 and T2 output signals are disabled and the correct value is assigned to the OPCODE
             STATE_ALU_EXEC: begin
                l_r_t1_oe = 0;
                l_r_t2_oe = 0;
                if (!i_ir[1]) begin
                    // Operation code verification
                    case(i_ir[6:4])
                        3'b100: begin
                            l_r_opcode = 4'd3;
                        end
                        3'b101: begin
                            l_r_opcode = 4'd4;
                        end
                        3'b110: begin
                            l_r_opcode = 4'd5;
                        end
                    endcase
                end
                else begin
                    // Operation code verification
                    case(i_ir[6:4])
                        3'b001: begin
                            l_r_opcode = 4'd0;
                        end
                        3'b100: begin
                            l_r_opcode = 4'd1;
                        end
                        3'b101: begin
                            l_r_opcode = 4'd2;
                        end
                    endcase
                end
                l_r_next_state = STATE_ALU_OUT;
             end
             // ALU output signal is enabled
             STATE_ALU_OUT: begin
                l_r_alu_oe = 1;
                l_r_next_state = STATE_RESTART;
             end
             // ALU output signal is disabled and the loop restarts
             STATE_RESTART: begin
                l_r_alu_oe = 0;
                l_r_next_state = STATE_INITIAL;
             end
        endcase
    end

    // Assign auxiliary reg variables to wires
    assign l_w_t1_we = l_r_t1_we;
    assign l_w_t1_oe = l_r_t1_oe;
    assign l_w_t2_we = l_r_t2_we;
    assign l_w_t2_oe = l_r_t2_oe;
    assign l_w_opcode = l_r_opcode;
    assign l_w_alu_oe = l_r_alu_oe;

endmodule