ex4_55

//BCD Add Sub
module BCD_Add_Sub(output[3:0] sum_diff,output carry_borrow,input[3:0] a,b,input Mode);
    wire[3:0] b_comp;
    wire[3:0] mux_output;

    Nines_Complement m0(b_comp,b);
    quad_mux21 m1(mux_output,b,b_comp,Mode);
    BCD_Adder m2(sum_diff,carry_borrow,a,mux_output,Mode);
endmodule

//4_54 9's
module Nines_Complement(output reg[3:0]comp,input[3:0]bcd);
    always @(bcd)
        case (bcd)
            4'd0:comp=4'd9;
            4'd1:comp=4'd8;
            4'd2:comp=4'd7;
            4'd3:comp=4'd6;
            4'd4:comp=4'd5;
            4'd5:comp=4'd4;
            4'd6:comp=4'd3;
            4'd7:comp=4'd2;
            4'd8:comp=4'd1;
            4'd9:comp=4'd0;
            default: comp=4'b1111;
        endcase
endmodule

//4.38
module quad_mux21(output[3:0]Y,input[3:0] A,B,input Select);
    //多工
    assign Y=Select ? B:A;
endmodule

module BCD_Adder(output[3:0] sum,output carry_out,input[3:0]a,b,input c_in);
    wire[3:0] z;
    wire c_out1,c_out2,w1,w2;
    wire[3:0] y;

    supply0 gnd;
    //For fix (when value is over 1001)
    //CarryOut=cout+z3z2+z3z1;
    and g0(w1,z[3],z[2]);
    and g1(w2,z[3],z[1]);
    or g2(carry_out,c_out1,w1,w2);

    assign y={1'b0,carry_out,carry_out,1'b0}; //Detect i f the value need fix

    //可用cla_4bit;
    Add_4bit m0(z,c_out1,a,b,c_in);

    Add_4bit m1(sum,c_out2,z,y,gnd); //For fix
endmodule

module Add_4bit(output[3:0]s,output c4,input[3:0] a,b,input c0);
   assign {c4,s}=a+b+c0;
endmodule

//前瞻
module cla_4bit(output[3:0]s,output c4,input[3:0]a,b,input c0);
    wire[3:0]p,g;
    HalfAdder M0(p[0],g[0],a[0],b[0]);
    HalfAdder M1(p[1],g[1],a[1],b[1]);
    HalfAdder M2(p[2],g[2],a[2],b[2]);
    HalfAdder M3(p[3],g[3],a[3],b[3]);

    assign c1=g[0]|(p[0]&c0);
    assign c2=g[1]|(p[1]&g[0])|(p[1]&p[0]&c0);
    assign c3=g[2]|(p[2]&g[1])|(p[2]&p[1]&g[0])|(p[2]&p[1]&p[0]&c0);
    assign c4=g[3]|(p[3]&g[2])|(p[3]&p[2]&g[1])|(p[3]&p[2]&p[1]&g[0]) | (p[3]&p[2]&g[1]&g[0]&c0);

    assign s[3]=c3^p[3];
    assign s[2]=c2^p[2];
    assign s[1]=c1^p[1];
    assign s[0]=c0^p[0];

endmodule


module HalfAdder(output s,c,input a,b);
    xor G0(s,a,b);
    and G1(c,a,b);
endmodule

module FullAdder(output s,co,input a,b,ci);
    wire s1,c1,c2;
    HalfAdder M0(s1,c1,a,b);
    HalfAdder M1(s,c2,s1,ci);
    or G0(co,c1,c2);
endmodule

//TestBench;
module t_BCD_Add_Sub();
    reg[3:0] a,b;
    reg Mode;
    wire[3:0] sum;
    wire c_out;

    BCD_Add_Sub m0(sum,c_out,a,b,Mode);
    //BCD_Adder m0(sum,c_out,a,b,Mode);
    initial fork
        Mode=0;
        a=4'b1001;
        b=4'd0101;
        #20
          a=4'b0100;
          #40
          a=4'b0011;
          Mode=1;
          #60
          a=4'b0111;
        #80 $finish;
    join
endmodule