Lab07 - Ej07 - Completo

module FSM (input A, clk, reset, output Y, output [1:0] state, next_state);

    reg [1:0] rstate, rnext_state;
    reg rY;
    parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;

    // Next State Logic
    always @ (A or rstate) begin
        case (rstate)
            S0:
                if (A)
                    rnext_state <= S1;
                else
                    rnext_state <= S0;
            S1:
                if (A)
                    rnext_state <= S1;
                else
                    rnext_state <= S2;
            S2:
                if (A)
                    rnext_state <= S3;
                else
                    rnext_state <= S0;
            S3:
                if (A)
                    rnext_state <= S1;
                else
                    rnext_state <= S0;
        endcase
    end

    // Flip flops
    always @ (posedge clk or posedge reset)
        if (reset)
            rstate <= S0;
        else
            rstate <= rnext_state;

    // Outputs Logic
    always @ (rstate)
        case (rstate)
            S0: rY = 0;
            S1: rY = 0;
            S2: rY = 0;
            S3: rY = 1;
            default: rY = 0;
        endcase



    // Wire output assignment
    assign state = rstate;
    assign next_state = rnext_state;
    assign Y = rY;

endmodule



module tb();

    // Inputs
    reg A, clk, reset;
    // Outputs
    wire Y;
    wire [1:0] state, next_state;

    // Module instantiation
    FSM U1 (A, clk, reset, y, state, next_state);

    initial begin
        A = 0; clk = 1; reset = 0;
        #2 reset = 1;
        #2 reset = 0;
        #18 A = 1;
        #10 A = 0;
        #10 A = 1;
        #40 A = 0;
        #40 A = 1;
        #10 A = 0;
        #10 A = 1;
        #10 A = 0;
        #10 A = 1;
        #10 A = 0;
        #10 A = 1;
    end

    initial
        #200 $finish;

    initial begin
        $dumpfile("timing.vcd");
        $dumpvars(0, tb);
    end

    always
        #5 clk = ~clk;

endmodule