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- ++ zephyr-on-litex-vexriscv/make.py --build --board litex_export_verilog --csr-json=csr.json --sys-clk-freq=45000000 --spi-flash-part W25Q128JV
- usage: {'description': 'LiteX SoC on Arty A7 and SDI-MIPI Bridge'} [-h] [--log-filename LOG_FILENAME]
- [--log-level LOG_LEVEL] [--toolchain TOOLCHAIN]
- --board BOARD [--build] [--variant VARIANT] [--load]
- [--sys-clk-freq SYS_CLK_FREQ]
- [--spi-flash-init SPI_FLASH_INIT]
- [--spi-data-width SPI_DATA_WIDTH]
- [--spi-clk-freq SPI_CLK_FREQ] [--local-ip LOCAL_IP]
- [--remote-ip REMOTE_IP] [--output-dir OUTPUT_DIR]
- [--gateware-dir GATEWARE_DIR]
- [--software-dir SOFTWARE_DIR]
- [--include-dir INCLUDE_DIR]
- [--generated-dir GENERATED_DIR]
- [--build-backend BUILD_BACKEND] [--no-compile]
- [--no-compile-software] [--no-compile-gateware]
- [--soc-csv SOC_CSV] [--soc-json SOC_JSON]
- [--soc-svd SOC_SVD] [--memory-x MEMORY_X] [--doc]
- [--bios-lto]
- [--bios-console {full,no-history,no-autocomplete,lite,disable}]
- [--synth-mode SYNTH_MODE]
- [--vivado-synth-directive VIVADO_SYNTH_DIRECTIVE]
- [--vivado-opt-directive VIVADO_OPT_DIRECTIVE]
- [--vivado-place-directive VIVADO_PLACE_DIRECTIVE]
- [--vivado-post-place-phys-opt-directive VIVADO_POST_PLACE_PHYS_OPT_DIRECTIVE]
- [--vivado-route-directive VIVADO_ROUTE_DIRECTIVE]
- [--vivado-post-route-phys-opt-directive VIVADO_POST_ROUTE_PHYS_OPT_DIRECTIVE]
- [--vivado-max-threads VIVADO_MAX_THREADS]
- [--yosys-nowidelut] [--yosys-abc9] [--yosys-flow3]
- [--yosys-quiet] [--nextpnr-timingstrict]
- [--nextpnr-ignoreloops] [--nextpnr-seed NEXTPNR_SEED] [--nexus-es-device]
- {'description': 'LiteX SoC on Arty A7 and SDI-MIPI Bridge'}: error: unrecognized arguments: --spi-flash-part W25Q128JV
- vrangan@ASUS-STRIX-B550:/mnt/e/Data/local_github/rtl_tinynx33u$
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