I2S_transmitter

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02/25/2024 06:29:54 PM
// Design Name:
// Module Name: I2S_receiver
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

module I2S_receiver
(
    input wire clk,
    input wire rstn,
    input wire en,
    input wire lrclk,
    input wire bclk,
    input wire sdi,

    output reg [23:0] adc_data,
    output wire adc_valid_l ,
    output wire adc_valid_r
);

// LRCLK edge detection
reg [2:0] lrclk_reg;
wire lrclk_rising;
wire lrclk_falling;
always @ (posedge clk)
begin
    if(rstn == 1'b0)
        lrclk_reg <= 3'b000;
    else
        lrclk_reg <= {lrclk_reg[1:0], lrclk};
end
assign lrclk_rising = (lrclk_reg == 3'b011);
assign lrclk_falling = (lrclk_reg == 3'b100);

//BCLK edge detection
reg [2:0] bclk_reg;
wire bclk_rising;
wire bclk_falling;
always @ (posedge clk)
begin
    if(rstn == 1'b0)
        bclk_reg <= 3'b000;
    else
        bclk_reg <= {bclk_reg[1:0], bclk};
end
assign bclk_rising = (bclk_reg == 3'b011);
assign bclk_falling = (bclk_reg == 3'b100);

//Shift register handling
always @ (posedge clk)
begin
    if(rstn == 1'b0)
        adc_data <= 24'd0;
    else if (bclk_rising == 1'b1)
        adc_data <= {adc_data[22:0], sdi};
end

//L valid signal generation
assign adc_valid_l = lrclk_falling && en;

//R valid signal generation
assign adc_valid_r = lrclk_rising && en;

endmodule