D FLIP-FLOP RESET SYNC

-- design.vhd

library IEEE;
use IEEE.std_logic_1164.all;

entity d_flipflop_wReset_sync is
    port(reset, clock, D : in std_logic;
         Q, Qn : out std_logic);
end entity d_flipflop_wReset_sync;

architecture d_flipflop_wReset_sync_arch of d_flipflop_wReset_sync is
begin
    process(clock)
    begin
        if(clock'event and clock = '1') then
            if(reset = '1') then
                Q <= '0';
                Qn <= '0';
            elsif(reset = '0' and D = '0') then
                Q <= D;
                Qn <= not D;
            elsif(reset = '0' and D = '1') then
                Q <= D;
                Qn <= not D;
            end if;
        end if;
    end process;
end architecture d_flipflop_wReset_sync_arch;


-- testbench.vhd

library IEEE;
use IEEE.std_logic_1164.all;

entity d_flipflop_wReset_sync_tb is
end entity d_flipflop_wReset_sync_tb;

architecture d_flipflop_wReset_sync_tb_arch of d_flipflop_wReset_sync_tb is
    signal reset1, clock1, D1, Q1, Qn1 : std_logic;
begin
    DUT1 : entity work.d_flipflop_wReset_sync(d_flipflop_wReset_sync_arch)
           port map(reset1, clock1, D1, Q1, Qn1);

    CLOCK : process
    begin
        clock1 <= '0'; wait for 10ns;
        clock1 <= '1'; wait for 10ns;
    end process CLOCK;

    STIMULUS : process
    begin
        reset1 <= '0'; D1 <= '0'; wait for 10ns;
        reset1 <= '1'; D1 <= '0'; wait for 10ns;
        reset1 <= '0'; D1 <= '0'; wait for 10ns;
        reset1 <= '1'; D1 <= '0'; wait for 10ns;
        reset1 <= '0'; D1 <= '1'; wait for 10ns;
        reset1 <= '1'; D1 <= '1'; wait for 10ns;
        reset1 <= '0'; D1 <= '1'; wait for 10ns;
        reset1 <= '1'; D1 <= '1'; wait for 10ns;
        reset1 <= '0'; D1 <= 'X'; wait for 10ns;
        reset1 <= '1'; D1 <= 'X'; wait for 10ns;
        reset1 <= '0'; D1 <= 'X'; wait for 10ns;
        reset1 <= '0'; D1 <= 'X'; wait for 10ns;
    end process STIMULUS;
end architecture d_flipflop_wReset_sync_tb_arch;