ac lab 11

module rgst #(
    parameter w=8
)(
    input clk, rst_b, ld, clr, input [w-1:0] d, output reg [w-1:0] q
);
    always @ (posedge clk, negedge rst_b)
        if (!rst_b)                 q <= 0;
        else if (clr)               q <= 0;
        else if (ld)                q <= d;
endmodule

module mlopadd(
  input clk, rst_b,
  input[6:0] x,
  output reg[13:0] a
);
  wire[7:0] var;
  rgst #(.w(8)) inst1(.clk(clk), .rst_b(rst_b), .ld(1'd1), .clr(1'd0), .d(x), .q(var));
  rgst #(.w(14)) inst2(.clk(clk), .rst_b(rst_b), .ld(1'd1), .clr(1'd0), .d(a + var), .q(a));
endmodule

module mlopadd_tb;
  reg clk, rst_b;
  reg[7:0] x;
  wire[13:0] a;
  mlopadd inst().clk(clk), .rst(rst_b), .x(x), .a(a));
  localparam CLK_PERIOD=100, RUNNING_CYCLES=101, RST_DURATION=25;
  initial begin
    $display("time\tclk\trst_b\tx\ta");
    $monitor("%5t\t%b\t%b\t%3d\t%5d", $time, clk, rst_b, x, a);
    clk=0;
    repeat (2*RUNNING_CYCLES) #(CLK_PERIOD/2) clk=~clk;
  end
  initial begin
    rst_b=0;
    #RST_DURATION rst_b=1;
  end
  integer k;
  initial begin
    x=1;
    for (k=3;k<200;k=k+2)
      #CLK_PERIOD x=k;
  end
endmodule