Lab 2 Group 11 VHDL Code

Counter5Periods.VHDL
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity Counter5Periods is
    port (
        clock: in std_logic;
        i_resetBar: in std_logic;
        output: out std_logic
    );
end entity Counter5Periods;

architecture Behavioral of Counter5Periods is
    signal counter: natural range 0 to 5 := 0; -- Counter initialized to 0

begin
    process (clock, i_resetBar)
    begin
        if i_resetBar = '0' then
            counter <= 0; -- Reset the counter to 0
            output <= '1'; -- Set output to '0' on reset
        elsif rising_edge(clock) then
            if counter < 3 then
                counter <= counter + 1; -- Increment the counter
                output <= '1'; -- Set output to '1' during the first 5 clock periods
            else
                output <= '0'; -- Set output to '0' after the first 5 clock periods
            end if;
        end if;
    end process;
end architecture Behavioral;

debouncer_2.VHDL
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY debouncer_2 IS
    PORT(
        i_resetBar      : IN    STD_LOGIC;
        i_clock         : IN    STD_LOGIC;
        i_raw           : IN    STD_LOGIC;
        o_clean         : OUT   STD_LOGIC);
END debouncer_2;

ARCHITECTURE rtl OF debouncer_2 IS
    SIGNAL con_vcc : STD_LOGIC;
    SIGNAL int_notQ1Output, int_q1Output, int_notD1Input, int_d1Input :STD_LOGIC;
    SIGNAL int_q2Output, int_notQ2Output, int_d2Input, int_debouncedRaw, int_feedback : STD_LOGIC;

    COMPONENT enARdFF_2
        PORT(
            i_resetBar  : IN    STD_LOGIC;
            i_d     : IN    STD_LOGIC;
            i_enable    : IN    STD_LOGIC;
            i_clock     : IN    STD_LOGIC;
            o_q, o_qBar : OUT   STD_LOGIC);
    END COMPONENT;
BEGIN
    con_vcc <= '1';
first: enARdFF_2
    PORT MAP (i_resetBar => i_resetBar,
              i_d => int_notD1Input,
              i_enable => con_vcc,
              i_clock => i_clock,
              o_q => int_q1Output,
              o_qBar => int_notQ1Output);

second: enARdFF_2
    PORT MAP (i_resetBar => i_resetBar,
              i_d => int_d2Input,
              i_enable => con_vcc,
              i_clock => i_clock,
              o_q => int_q2Output,
              o_qBar => int_notQ2Output);

    -- Internal concurrent signal assignment
    int_notD1Input <= not(int_d1Input);
    int_d1Input <= i_raw nand int_feedback;
    int_feedback <= int_q2Output or int_debouncedRaw;
    int_d2Input <= int_notQ1Output and int_notQ2Output and i_raw;
    int_debouncedRaw <= int_q2Output nor int_notQ1Output;

    --  Output Concurrent Signal Assignment
    o_clean <= int_debouncedRaw;

END rtl;


dec_7seg.VHDL
library ieee;
use  ieee.std_logic_1164.all;

ENTITY dec_7seg IS
    PORT(i_hexDigit : IN STD_LOGIC_VECTOR(3 downto 0);
         o_segment: OUT STD_LOGIC_VECTOR(0 to 6));
END dec_7seg;

ARCHITECTURE rtl OF dec_7seg IS
    SIGNAL int_segment_data : STD_LOGIC_VECTOR(6 DOWNTO 0);
BEGIN
    PROCESS  (i_hexDigit)
    BEGIN
        CASE i_hexDigit IS
                WHEN "0000" =>
                    int_segment_data <= "1111110";
                WHEN "0001" =>
                    int_segment_data <= "0110000";
                WHEN "0010" =>
                    int_segment_data <= "1101101";
                WHEN "0011" =>
                    int_segment_data <= "1111001";
                WHEN "0100" =>
                    int_segment_data <= "0110011";
                WHEN "0101" =>
                    int_segment_data <= "1011011";
                WHEN "0110" =>
                    int_segment_data <= "1011111";
                WHEN "0111" =>
                    int_segment_data <= "1110000";
                WHEN "1000" =>
                    int_segment_data <= "1111111";
                WHEN "1001" =>
                    int_segment_data <= "1111011";
                WHEN "1010" =>
                    int_segment_data <= "1110111";
                WHEN "1011" =>
                    int_segment_data <= "0011111";
                WHEN "1100" =>
                    int_segment_data <= "1001110";
                WHEN "1101" =>
                    int_segment_data <= "0111101";
                WHEN "1110" =>
                    int_segment_data <= "1001111";
                WHEN "1111" =>
                    int_segment_data <= "1000111";
            WHEN OTHERS =>
                    int_segment_data <= "0111110";
        END CASE;
    END PROCESS;

-- LED driver is inverted
o_segment <= NOT int_segment_data;

END rtl;


enARdFF_2.VHDL
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY enARdFF_2 IS
    PORT(
        i_resetBar  : IN    STD_LOGIC;
        i_d     : IN    STD_LOGIC;
        i_enable    : IN    STD_LOGIC;
        i_clock     : IN    STD_LOGIC;
        o_q, o_qBar : OUT   STD_LOGIC);
END enARdFF_2;

ARCHITECTURE rtl OF enARdFF_2 IS
    SIGNAL int_q : STD_LOGIC;

BEGIN

oneBitRegister:
PROCESS(i_resetBar, i_clock)
BEGIN
    IF (i_resetBar = '0') THEN
        int_q   <= '0';
    ELSIF (i_clock'EVENT and i_clock = '1') THEN
        IF (i_enable = '1') THEN
            int_q   <=  i_d;
        END IF;
    END IF;
END PROCESS oneBitRegister;

    --  Output Driver

    o_q     <=  int_q;
    o_qBar      <=  not(int_q);

END rtl;


enARdFF_2rev.VHDL
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY enARdFF_2rev IS
    PORT(
        i_resetBar  : IN    STD_LOGIC;
        i_d     : IN    STD_LOGIC;
        i_enable    : IN    STD_LOGIC;
        i_clock     : IN    STD_LOGIC;
        o_q, o_qBar : OUT   STD_LOGIC);
END enARdFF_2rev;

ARCHITECTURE rtl OF enARdFF_2rev IS
    SIGNAL int_q : STD_LOGIC;

BEGIN

oneBitRegister:
PROCESS(i_resetBar, i_clock)
BEGIN
    IF (i_resetBar = '0') THEN
        int_q   <= '1';
    ELSIF (i_clock'EVENT and i_clock = '1') THEN
        IF (i_enable = '1') THEN
            int_q   <=  i_d;
        END IF;
    END IF;
END PROCESS oneBitRegister;

    --  Output Driver

    o_q     <=  int_q and i_enable;
    o_qBar      <=  not(int_q) and i_enable;

END rtl;


Encoder2x1sl.VHDL
library ieee;
use ieee.std_logic_1164.all;

entity Encoder2x1sl is
    port (
        I1, I0: in std_logic;
        O: out std_logic_vector(1 downto 0)
    );
end;

architecture rtl of Encoder2x1sl is
begin
    process(I1, I0)
    begin
        if (I1 = '1') then
            O <= "01";
        elsif (I0 = '1') then
            O <= "10";
        else
            O <= "00"; -- Optionally handle the case when neither input is active.
        end if;
    end process;
end architecture rtl;


Encoder2x1sr.VHDL
library ieee;
use ieee.std_logic_1164.all;

entity Encoder2x1sr is
    port (
        I1, I0: in std_logic;
        O: out std_logic_vector(1 downto 0)
    );
end;

architecture rtl of Encoder2x1sr is
begin
    process(I1, I0)
    begin
        if (I1 = '1') then
            O <= "01";
        elsif (I0 = '1') then
            O <= "11";
        else
            O <= "00"; -- Optionally handle the case when neither input is active.
        end if;
    end process;
end architecture rtl;


fourBitAdder.VHDL
library ieee;
use ieee.std_logic_1164.all;

entity fourBitAdder is
    port (
        i_X, i_Y: in std_logic_vector(3 downto 0);
        i_Cin: in std_logic;
        o_S: out std_logic_vector(3 downto 0);
        o_Cout: out std_logic;
        o_P, o_G: out std_logic;
        o_V, o_Z: out std_logic
    );
end;

architecture Structural of fourBitAdder is
    component oneBitFullAdder
        port (
            i_X, i_Y: in std_logic;
            i_Cin: in std_logic;
            o_S: out std_logic;
            o_Cout: out std_logic;
            o_P, o_G: out std_logic
        );
    end component;

    component LookaheadCarryUnit
        port (
            i_P, i_G: in std_logic_vector(3 downto 0);
            i_Cin: in std_logic;
            o_PG, o_GG: out std_logic;
            o_C: out std_logic_vector(4 downto 0)
        );
    end component;

    signal signalFullAdderCarry: std_logic_vector(4 downto 0);
    signal signalFullAdderG, signalFullAdderP: std_logic_vector(3 downto 0);
    signal signalS: std_logic_vector(3 downto 0);
begin
    generateFullAdder:
        for i in 3 downto 0 generate
            fullAdderInst: oneBitFullAdder
                port map (
                    i_X => i_X(i),
                    i_Y => i_Y(i),
                    i_Cin => signalFullAdderCarry(i),
                    o_S => signalS(i),
                    o_P => signalFullAdderP(i),
                    o_G => signalFullAdderG(i)
                );
        end generate;

    lookaheadCarryUnitInst: LookaheadCarryUnit
        port map (
            i_P => signalFullAdderP,
            i_G => signalFullAdderG,
            i_Cin => i_Cin,
            o_C => signalFullAdderCarry,
            o_PG => o_P,
            o_GG => o_G
        );

    o_S <= signalS;
    o_Cout <= signalFullAdderCarry(4);
    o_V <= signalFullAdderCarry(4) xor signalFullAdderCarry(3);
    o_Z <= not (signalS(3) or signalS(2) or signalS(1) or signalS(0));
end;



fourBitAdderSubtractor.VHDL
library ieee;
use ieee.std_logic_1164.all;

entity fourBitAdderSubtractor is
    port (
        i_X, i_Y: in std_logic_vector(3 downto 0);
        i_SUB: in std_logic;
        o_S: out std_logic_vector(3 downto 0);
        o_Cout: out std_logic;
        o_V, o_Z: out std_logic
    );
end;

architecture Structural of fourBitAdderSubtractor is
    component fourBitAdder
        port (
            i_X, i_Y: in std_logic_vector(3 downto 0);
            i_Cin: in std_logic;
            o_S: out std_logic_vector(3 downto 0);
            o_Cout: out std_logic;
            o_P, o_G: out std_logic;--lookahead
            o_V, o_Z: out std_logic--overflow flag(V); zero flag(Z)
        );
    end component;

    signal signalY: std_logic_vector(3 downto 0);
begin
    generateSignalY:
        for i in 3 downto 0 generate
            signalY(i) <= i_Y(i) xor i_SUB;
        end generate;

    adder4Inst: fourBitAdder
        port map (
            i_X => i_X,
            i_Y => signalY,
            i_Cin => i_SUB,
            o_S => o_S,
            o_Cout => o_Cout,
            o_V => o_V,
            o_Z => o_Z
        );
end;



Gnd4bit.VHDL
library ieee;
use ieee.std_logic_1164.all;

entity Gnd4bit is
    port(
        OUTPUT: out std_logic_vector(3 downto 0)
    );
end;

architecture Rtl of Gnd4bit is
    begin
    OUTPUT <= "0000";
end Rtl;




LookaheadCarryUnit.VHDL
library ieee;
use ieee.std_logic_1164.all;

entity LookaheadCarryUnit is
    port (
        i_P, i_G: in std_logic_vector(3 downto 0);
        i_Cin: in std_logic;
        o_PG, o_GG: out std_logic;
        o_C: out std_logic_vector(4 downto 0)
    );
end;

architecture Structural of LookaheadCarryUnit is
begin
    o_C(0) <= i_Cin;
    o_C(1) <= i_G(0) or (i_P(0) and i_Cin);
    o_C(2) <= i_G(1) or (i_P(1) and i_G(0)) or (i_P(1) and i_P(0) and i_Cin);
    o_C(3) <= i_G(2) or (i_P(2) and i_G(1)) or (i_P(2) and i_P(1) and i_G(0)) or (i_P(2) and i_P(1) and i_P(0) and i_Cin);
    o_C(4) <= i_G(3) or (i_P(3) and i_G(2)) or (i_P(3) and i_P(2) and i_G(1)) or (i_P(3) and i_P(2) and i_P(1) and i_G(0)) or (i_P(3) and i_P(2) and i_P(1) and i_P(0) and i_Cin);

    o_PG <= i_P(3) and i_P(2) and i_P(1) and i_P(0);
    o_GG <= i_G(3) or (i_P(3) and i_G(2)) or (i_P(3) and i_P(2) and i_G(1)) or (i_P(3) and i_P(2) and i_P(1) and i_G(0));
end;



LSBTaker.VHDL
library ieee;
use ieee.std_logic_1164.all;

entity LSBTaker is
    port(
        INPUT: in std_logic_vector(3 downto 0);
          OUTPUT: out std_logic
    );
end;

architecture Rtl of LSBTaker is
    begin
    OUTPUT <= INPUT(0);
end Rtl;



MUX4bit2x1.VHDL
library ieee;
use ieee.std_logic_1164.all;

entity MUX4bit2x1 is
    port(
        I1,I0: in std_logic_vector(3 downto 0);
        OUTPUT: out std_logic_vector(3 downto 0);
        C: in std_logic
    );
end;

architecture Rtl of MUX4bit2x1 is
    begin
    OUTPUT(3) <= (I1(3) AND C) OR (I0(3) AND not(C));
     OUTPUT(2) <= (I1(2) AND C) OR (I0(2) AND not(C));
     OUTPUT(1) <= (I1(1) AND C) OR (I0(1) AND not(C));
     OUTPUT(0) <= (I1(0) AND C) OR (I0(0) AND not(C));
end Rtl;



MUX4x1.VHDL
library ieee;
use ieee.std_logic_1164.all;

entity MUX4x1 is
    port(
        INPUT: in std_logic_vector(3 downto 0);
        OUTPUT: out std_logic;
        C: in std_logic_vector(1 downto 0)
    );
end;

architecture Rtl of MUX4x1 is
    begin
    OUTPUT <= (INPUT(3) AND C(1) AND C(0)) OR
                    (INPUT(2) AND C(1) AND not(C(0))) OR
                    (INPUT(1) AND not(C(1)) AND C(0)) OR
                    (INPUT(0) AND not(C(1)) AND not(C(0)));
end Rtl;



MUX8bit4x1.VHDL
library ieee;
use ieee.std_logic_1164.all;

entity MUX8bit4x1 is
    port (
        I3, I2, I1, I0: in std_logic_vector(7 downto 0);
        O: out std_logic_vector(7 downto 0);
        C: in std_logic_vector(1 downto 0)
    );
end;

ARCHITECTURE rtl OF MUX8bit4x1 IS
    BEGIN

        O(0) <= (C(1)AND C(0) AND I3(0)) OR (not(C(1))AND C(0) AND  I2(0)) OR (C(1) AND not(C(0)) AND I1(0)) OR(not(C(1)) AND not(C(0)) AND I0(0));
        O(1) <= (C(1)AND C(0) AND I3(1)) OR (not(C(1))AND C(0) AND  I2(1)) OR (C(1) AND not(C(0)) AND I1(1)) OR(not(C(1)) AND not(C(0)) AND I0(1));
        O(2) <= (C(1)AND C(0) AND I3(2)) OR (not(C(1))AND C(0) AND  I2(2)) OR (C(1) AND not(C(0)) AND I1(2)) OR(not(C(1)) AND not(C(0)) AND I0(2));
        O(3) <= (C(1)AND C(0) AND I3(3)) OR (not(C(1))AND C(0) AND  I2(3)) OR (C(1) AND not(C(0)) AND I1(3)) OR(not(C(1)) AND not(C(0)) AND I0(3));
        O(4) <= (C(1)AND C(0) AND I3(4)) OR (not(C(1))AND C(0) AND  I2(4)) OR (C(1) AND not(C(0)) AND I1(4)) OR(not(C(1)) AND not(C(0)) AND I0(4));
        O(5) <= (C(1)AND C(0) AND I3(5)) OR (not(C(1))AND C(0) AND  I2(5)) OR (C(1) AND not(C(0)) AND I1(5)) OR(not(C(1)) AND not(C(0)) AND I0(5));
        O(6) <= (C(1)AND C(0) AND I3(6)) OR (not(C(1))AND C(0) AND  I2(6)) OR (C(1) AND not(C(0)) AND I1(6)) OR(not(C(1)) AND not(C(0)) AND I0(6));
        O(7) <= (C(1)AND C(0) AND I3(7)) OR (not(C(1))AND C(0) AND  I2(7)) OR (C(1) AND not(C(0)) AND I1(7)) OR(not(C(1)) AND not(C(0)) AND I0(7));

    END rtl;



oneBitFullAdder.VHDL
library ieee;
use ieee.std_logic_1164.all;

entity oneBitFullAdder is
    port (
        i_X, i_Y: in std_logic;
        i_Cin: in std_logic;
        o_S: out std_logic;
        o_Cout: out std_logic;
        o_P, o_G: out std_logic
    );
end oneBitFullAdder;

architecture Structural of oneBitFullAdder is
begin
    o_S <= i_X xor i_Y xor i_Cin;
    o_Cout <= (i_X and i_Y) or (i_Cin and i_X) or (i_Cin and i_Y);
    o_P <= i_X or i_Y;
    o_G <= i_X and i_Y;
end;


Register4.VHDL
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY Register4 IS
    PORT(
        i_resetBar, i_load  : IN    STD_LOGIC;
        i_clock         : IN    STD_LOGIC;
        i_Value         : IN    STD_LOGIC_VECTOR(3 downto 0);
        o_Value         : OUT   STD_LOGIC_VECTOR(3 downto 0));
END Register4;

ARCHITECTURE rtl OF Register4 IS
    SIGNAL int_Value, int_notValue : STD_LOGIC_VECTOR(3 downto 0);

    COMPONENT enARdFF_2
        PORT(
            i_resetBar  : IN    STD_LOGIC;
            i_d     : IN    STD_LOGIC;
            i_enable    : IN    STD_LOGIC;
            i_clock     : IN    STD_LOGIC;
            o_q, o_qBar : OUT   STD_LOGIC);
    END COMPONENT;

BEGIN

msb: enARdFF_2
    PORT MAP (i_resetBar => i_resetBar,
              i_d => i_Value(3),
              i_enable => i_load,
              i_clock => i_clock,
              o_q => int_Value(3),
              o_qBar => int_notValue(3));

qsb: enARdFF_2
    PORT MAP (i_resetBar => i_resetBar,
              i_d => i_Value(2),
              i_enable => i_load,
              i_clock => i_clock,
              o_q => int_Value(2),
              o_qBar => int_notValue(2));

wsb: enARdFF_2
    PORT MAP (i_resetBar => i_resetBar,
              i_d => i_Value(1),
              i_enable => i_load,
              i_clock => i_clock,
              o_q => int_Value(1),
              o_qBar => int_notValue(1));

esb: enARdFF_2
    PORT MAP (i_resetBar => i_resetBar,
              i_d => i_Value(0),
              i_enable => i_load,
              i_clock => i_clock,
              o_q => int_Value(0),
              o_qBar => int_notValue(0));


    -- Output Driver
    o_Value     <= int_Value;

END rtl;




shiftleftR.VHDL
library ieee;
use ieee.std_logic_1164.all;

entity shiftleftR is
    port (
        I0: in std_logic;
        O: out std_logic_vector(1 downto 0)
    );
end;

architecture rtl of shiftleftR is
begin
    process(I0)
    begin
        if (I0 = '1') then
            O <= "10";
          else
            O <= "00"; -- Optionally handle the case when neither input is active.
        end if;
    end process;
end architecture rtl;



ShiftRegister4.VHDL
library ieee;
use ieee.std_logic_1164.all;

entity ShiftRegister4 is
    port (
        CLK, RESETN: in std_logic;
        MODE: in std_logic_vector(1 downto 0);
        SERIAL_IN_LEFT, SERIAL_IN_RIGHT: in std_logic;
        PARALLEL_IN: in std_logic_vector(3 downto 0);
        PARALLEL_OUT: out std_logic_vector(3 downto 0)
    );
    -- MODE: 00 for latching, 01 for parallel loading, 10 for shifting left, 11 for shifting right
end;

architecture Structural of ShiftRegister4 is
    component enARdFF_2 is
        port (
            i_resetBar: in std_logic;
            i_d: in std_logic;
            i_enable: in std_logic;
            i_clock: in std_logic;
            o_q, o_qBar: out std_logic
        );
    end component;

    component MUX4x1 is
        port(
            INPUT: in std_logic_vector(3 downto 0);
            OUTPUT: out std_logic;
            C: in std_logic_vector(1 downto 0)
        );
    end component;

    signal signalDFFOutput: std_logic_vector(3 downto 0);
    signal signalMUXOutput: std_logic_vector(3 downto 0);
    signal signalMUXInputLeftShift: std_logic_vector(3 downto 0);
    signal signalMUXInputRightShift: std_logic_vector(3 downto 0);
begin
    signalMUXInputLeftShift(0) <= SERIAL_IN_RIGHT;
    signalMUXInputLeftShift(3 downto 1) <= signalDFFOutput(2 downto 0);
    signalMUXInputRightShift(3) <= SERIAL_IN_LEFT;
    signalMUXInputRightShift(2 downto 0) <= signalDFFOutput(3 downto 1);

    generateMUX: for i in 3 downto 0 generate
        MUX4x1Inst: MUX4x1
            port map (
                INPUT(3) => signalMUXInputRightShift(i),
                INPUT(2) => signalMUXInputLeftShift(i),
                INPUT(1) => PARALLEL_IN(i),
                INPUT(0) => signalDFFOutput(i),
                OUTPUT => signalMUXOutput(i),
                C => MODE
            );
    end generate;

    generateDFF: for i in 3 downto 0 generate
        DFFInst: enARdFF_2
            port map (
                i_resetBar => RESETN,
                i_d => signalMUXOutput(i),
                i_enable => '1',
                i_clock => CLK,
                o_q => signalDFFOutput(i)
            );
    end generate;

    PARALLEL_OUT <= signalDFFOutput;
end;



ShiftRegister8.VHDL
library ieee;
use ieee.std_logic_1164.all;

entity ShiftRegister8 is
    port (
        CLK, RESETN: in std_logic;
        MODE: in std_logic_vector(1 downto 0);
        SERIAL_IN_LEFT, SERIAL_IN_RIGHT: in std_logic;
        PARALLEL_IN: in std_logic_vector(7 downto 0);
        PARALLEL_OUT: out std_logic_vector(7 downto 0)
    );
    -- MODE: 00 for latching, 01 for parallel loading, 10 for shifting left, 11 for shifting right
end;

architecture Structural of ShiftRegister8 is
    component enARdFF_2 is
        port (
            i_resetBar: in std_logic;
            i_d: in std_logic;
            i_enable: in std_logic;
            i_clock: in std_logic;
            o_q, o_qBar: out std_logic
        );
    end component;

    component MUX4x1 is
        port(
            INPUT: in std_logic_vector(3 downto 0);
            OUTPUT: out std_logic;
            C: in std_logic_vector(1 downto 0)
        );
    end component;

    signal signalDFFOutput: std_logic_vector(7 downto 0);
    signal signalMUXOutput: std_logic_vector(7 downto 0);
    signal signalMUXInputLeftShift: std_logic_vector(7 downto 0);
    signal signalMUXInputRightShift: std_logic_vector(7 downto 0);
begin
    signalMUXInputLeftShift(0) <= SERIAL_IN_RIGHT;
    signalMUXInputLeftShift(7 downto 1) <= signalDFFOutput(6 downto 0);
    signalMUXInputRightShift(7) <= SERIAL_IN_LEFT;
    signalMUXInputRightShift(6 downto 0) <= signalDFFOutput(7 downto 1);

    generateMUX: for i in 7 downto 0 generate
        MUX4x1Inst: MUX4x1
            port map (
                INPUT(3) => signalMUXInputRightShift(i),
                INPUT(2) => signalMUXInputLeftShift(i),
                INPUT(1) => PARALLEL_IN(i),
                INPUT(0) => signalDFFOutput(i),
                OUTPUT => signalMUXOutput(i),
                C => MODE
            );
    end generate;

    generateDFF: for i in 7 downto 0 generate
        DFFInst: enARdFF_2
            port map (
                i_resetBar => RESETN,
                i_d => signalMUXOutput(i),
                i_enable => '1',
                i_clock => CLK,
                o_q => signalDFFOutput(i)
            );
    end generate;

    PARALLEL_OUT <= signalDFFOutput;
end;