module tb4();

    reg clk, rst, switch_en;
    reg [3:0] r_switches, g_switches, b_switches;
    wire [3:0] pix_r, pix_g, pix_b;
    wire hsync, vsync;

    // instantiation
    vga_out uut(
        .clk(clk),
        .rst(rst),
        .switch_en(switch_en),
        .r_switches(r_switches),
        .g_switches(g_switches),
        .b_switches(b_switches),
        .pix_r(pix_r),
        .pix_g(pix_g),
        .pix_b(pix_b),
        .hsync(hsync),
        .vsync(vsync)
    );

    // Initial block for setting up inputs
    initial begin
        clk = 1'b0;
        rst = 1'b1;
        switch_en = 1'b1; // Assuming you want to enable the switches initially
        r_switches = 4'b1111;
        g_switches = 4'b0000;
        b_switches = 4'b0000;

        // Add more testbench logic as needed

        // Simulation time for observation
        #1000;
        $finish;
    end

    // Clock generation
    always #5 clk = ~clk;

endmodule