DNALock ise report

Started : "Synthesize - XST".
Running xst...
Command Line: xst -intstyle ise -ifn "C:/Projects/Anti clone S6/code/test1/DNATest/testDNALock.xst" -ofn "C:/Projects/Anti clone S6/code/test1/DNATest/testDNALock.syr"
Reading design: testDNALock.prj

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*                          HDL Parsing                                  *
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Parsing VHDL file "C:\Projects\Anti clone S6\code\test1\DNATest\IOCutOut.vhd" into library work
Parsing entity <IOCutOut>.
Parsing architecture <Behavioral> of entity <iocutout>.
WARNING:HDLCompiler:1369 - "C:\Projects\Anti clone S6\code\test1\DNATest\IOCutOut.vhd" Line 66: Possible infinite loop; process does not have a wait statement
Parsing VHDL file "C:\Projects\Anti clone S6\code\test1\DNATest\DNALock.vhd" into library work
Parsing entity <DNALock>.
INFO:HDLCompiler:1676 - "C:\Projects\Anti clone S6\code\test1\DNATest\DNALock.vhd" Line 36. declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output
Parsing architecture <Behavioral> of entity <dnalock>.
Parsing VHDL file "C:\Projects\Anti clone S6\code\test1\DNATest\testDNALock.vhd" into library work
Parsing entity <testDNALock>.
INFO:HDLCompiler:1676 - "C:\Projects\Anti clone S6\code\test1\DNATest\testDNALock.vhd" Line 53. declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output
Parsing architecture <Behavioral> of entity <testdnalock>.
INFO:HDLCompiler:1676 - "C:\Projects\Anti clone S6\code\test1\DNATest\testDNALock.vhd" Line 99. declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output

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*                            HDL Elaboration                            *
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Elaborating entity <testDNALock> (architecture <Behavioral>) from library <work>.

Elaborating entity <DNALock> (architecture <Behavioral>) from library <work>.
WARNING:HDLCompiler:1127 - "C:\Projects\Anti clone S6\code\test1\DNATest\DNALock.vhd" Line 71: Assignment to sr_readb ignored, since the identifier is never used
WARNING:HDLCompiler:92 - "C:\Projects\Anti clone S6\code\test1\DNATest\DNALock.vhd" Line 162: dna_clk_temp should be on the sensitivity list of the process
WARNING:HDLCompiler:1127 - "C:\Projects\Anti clone S6\code\test1\DNATest\DNALock.vhd" Line 145: Assignment to sr_clk ignored, since the identifier is never used
WARNING:HDLCompiler:92 - "C:\Projects\Anti clone S6\code\test1\DNATest\DNALock.vhd" Line 201: sr_out should be on the sensitivity list of the process

Elaborating entity <IOCutOut> (architecture <Behavioral>) from library <work>.

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*                           HDL Synthesis                               *
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Synthesizing Unit <testDNALock>.
    Related source file is "C:\Projects\Anti clone S6\code\test1\DNATest\testDNALock.vhd".
WARNING:Xst:647 - Input <CLK_98MHz> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2935 - Signal 'DNAVerify', unconnected in block 'testDNALock', is tied to its initial value (0).
    Summary:
    no macro.
Unit <testDNALock> synthesized.