CPE212-[Lab8.1] q4

module upperwg(g,q,x,clk,reset);
    input x,reset,clk;
    output [1:0]q;
    output g;
    wire nq0;

    uppernog ung(q,x,clk,reset);

    not not1(nq0,q[1]);
    and and1(g,x,q[0],nq0);
endmodule

module uppernog(q,x,clk,reset);
    input x,reset,clk;
    output [1:0]q;
    wire xorq,xorf,nq1;

    xor xor1(xorq,q[0],q[1]);
    xor xor2(xorf,x,xorq);

    not not1(nq1,q[0]);

    D_FF d0(q[1],xorf,clk,reset);
    D_FF d1(q[0],nq1,clk,reset);

endmodule

module D_FF(q,d,clk,reset);
    output q;
    input d,clk,reset;
    reg q;
    always @(posedge reset or negedge clk)
    if(reset)
        q <= 1'b0;
    else
        q <= d;
endmodule

module stimulus;
    wire [1:0]q;
    wire g;
    reg x,clk,reset;

    upperwg up1(g,q,x,clk,reset);

    initial
        begin
            x = 1'b0;
            clk = 1'b1;
            reset = 1'b1;
        end

    always #1 clk = ~clk;
    always #16 x = ~x;
    initial
        begin
            #10 reset = ~reset;
            #40 reset = ~reset;
        end
    initial #50 $finish;

    initial
        $monitor($time,"\treset = %d\tclk = %d\t\tx = %d\tq = %b\tg = %d",reset,clk,x,q,g);
endmodule